LC87F6D64A

No.A1007-3/19

AD Converter: 8 bits

× 8 channels

Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN)

• Noise rejection function

(Units of noise rejection filter: about 120

μs, when selecting a 32.768kHz crystal oscillator as a clock.)

• Supporting reception formats with a guide-pulse of half-clock/clock/none.

• Determines a end of reception by detecting a no-signal periods (No carrier).

(Supports same reception format with a different bit length.)

• X’tal HOLD mode release function

Watchdog Timer

• The watching timer period is set using an external RC.

• Watchdog timer can produce interrupt, system reset.

Clock Output Function

1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.

2) Able to output oscillation clock of sub clock.

Interrupts: 14 sources, 10 vector interrupts

• Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,

an equal or lower priority interrupt request is refused.

• If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.

In the case of equal priority levels, the vector with the lowest address takes precedence.

No.

Vector

Selectable Level

Interrupt Signal

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/remote control receiver

4

0001BH

H or L

INT3/Base timer 0/1

5

00023H

H or L

T0H

6

0002BH

H or L

7

00033H

H or L

SIO0

8

0003BH

H or L

SIO1

9

00043H

H or L

ADC

10

0004BH

H or L

Port0/T4/T5

• Priority Level: X>H>L

• For equal priority levels, vector with lowest address takes precedence.

Subroutine Stack Levels: 1024 levels maximum (Stack is located in RAM.)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

(5 tCYC execution time)

• 24 bits × 16 bits

(12 tCYC execution time)

• 16 bits ÷ 8 bits

(8 tCYC execution time)

• 24 bits ÷ 16 bits

(12 tCYC execution time)

Oscillation Circuits

• On-chip RC oscillation circuit for system clock use.

• On-chip CF oscillation circuit* for system clock use. (Rf built in)

• On-chip Crystal oscillation circuit* low speed system clock use. (Rf built in)

• Frequency variable RC oscillation circuit (internal) for system clock.

1) Adjustable in

±4% (typ) step from a selected center frequency.

2) Measures oscillation clock using a input signal from XT1 as a reference.

* The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of

commonness.