LC87F6D64A

No.A1007-4/19

System Clock Divider Function

• Able to reduce current consumption

Available minimum instruction cycle time: 300ns, 600ns, 1.2

μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs.

(Using 10MHz main clock)

Standby Function

• HALT mode

HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate

but VFD display and some serial transfer operations stop.

1) Oscillation circuits are not stopped automatically.

2) Release occurs on system reset or by interrupt.

• HOLD mode

HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped.

1) The CF, RC, X’tal and frequency variable RC oscillators automatically stop operation.

2) Release occurs on any of the following conditions.

(1) input to the reset pin goes “Low”

(2) a specified level is input to at least one of INT0, INT1, INT2

(3) an interrupt condition arises at port 0

• X’tal HOLD mode.

X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.

All peripheral circuits except the base-timer are stopped.

1) The CF, RC, frequency variable RC oscillation circuits stop automatically.

2) Crystal oscillator is maintained in its state at HOLD mode inception.

3) Release occurs on any of the following conditions.

(1) input to the reset pin goes “Low”

(2) Setting at least one of the INT0, INT1 and INT2 pins to the specified level

(3) Having an interrupt source established at port 0

(4) Having an interrupt source established in the base timer circuit

(5) Having an interrupt source established in the remote control receiver circuit

On-chip Debugger

• Supports software debugging with the IC mounted on the target board.

Package Form

• QFP80(14×14): Lead-free type

Development Tools

• On-chip debugger: TCB87- type-B + LC87F6D64A