AX5031 datasheet(18/36 Pages) ONSEMI

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Circuit Description

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AX5031

5.3.

SYSCLK Output

The SYSCLK pin outputs the reference clock signal divided by a programmable integer.

Divisions from 1 to 2048 are possible. For divider ratios > 1 the duty cycle is 50%. Bits

SYSCLK[3:0] in the PINCFG1 register set the divider ratio. The SYSCLK output can be disabled.

5.4.

Power-on-reset (POR)

AX5031 has an integrated power-on-reset block. No external POR circuit or signal is required.

After POR the AX5031 can be reset by SPI accesses, this is achieved by toggling the bit RST in

the PWRMODE register.

After POR or reset all registers are set to their default values.

5.5.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a fully integrated synthesizer, which

multiplies the reference frequency from the crystal oscillator to get the desired RF frequency.

The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as

fast settling times of 5 – 50 s depending on the settings (see section 4.3: AC Characteristics).

Fast settling times mean fast start-up, which enables low-power system design.

The frequency must be programmed to the desired carrier frequency.

The synthesizer loop bandwidth can be programmed, this serves three purposes:

1. Start-up time optimisation, start-up is faster for higher synthesizer loop bandwidths

2. TX spectrum optimisation, phase-noise at 300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths

3. Adaptation of the bandwidth to the data-rate. For transmission of FSK and MSK it is

required that the synthesizer bandwidth must be in the order of the data-rate.

AX5031 Datasheet(PDF) 18 Page - ON Semiconductor