JUPITER

2

CIRCUIT DESCRIPTION

The block diagram of the JUPITER filter is shown in

Fig. 3. Two tunable active low-pass gyrator filters are designed

with balanced I/Q inputs and outputs.

CDMA MODE

In CDMA mode the filter (F1 on Fig. 3) is a 7th order 0.1dB

ripple continuously tunable elliptic type with the corner frequency

tuned to 690kHz for best stop band attenuation and minimal

phase error (in the overall system). Variable gain stages after the

filter provide the gain control capability. Overall, each of the

CDMA I/Q channels has 45dB nominal voltage gain with the Q

channel having

±2dB gain adjustment range. Separate I/Q

frequency tuning functions are built into the device.

FM MODE

In FM mode the same filter is used; however, the biasing is

designed such that the current density in the transconductor cells

is reduced by a factor of 46, changing the filter’s cutoff frequency

to 15kHz. The filter characteristic of the main channel filter

(gyrator filter) remains the same, i.e. a 0.1dB 7th order elliptic. In

FM mode additional 2nd order Sallen and Key 0.1dB ripple

Chebeyshev filters (F2) are included in the signal path prior to the

gyrators. These improve the out-of-band blocking of the overall

filter. Different amplifiers are used in FM mode to those used in

CDMA mode to enable optimization of the gain distribution in FM

mode for current consumption and dynamic range.

OPERATION

Signal inputs are DC coupled in both CDMA and FM modes.

The device modes are selected by CMOS compatible logic

signals as shown in Table 2. An external resistor should be

connected between RTUNE and ground to set internal currents;

a resistor with a tolerance of 65% and a temperature coefficient

A test mode is provided for filter calibration. In this mode, a test

The test mode is designed to interface with the PLUTO baseband

processor, which can provide the test signal and I/QTUNE

voltages and calibrates the filters using an internal auto calibration

algorithm. The algorithm generates two test frequencies and

calibrates the filters to give the correct attenuation at the upper

frequency. The calibration is normally carried out in CDMA

mode: the FM filter performance is scaled accordingly.

Pins are provided for DC offset control for I and Q channels

(I_OFFSET, I_OFFSETB, Q_OFFSET and Q_OFFSETB). In

typical operation, the I_OFFSET/Q_OFFSET pins would be

controlled by a voltage derived from the baseband processor.

However, it is also possible to minimise the DC offset using

external components; this is primarily intended for test purposes.

These feedback components between IOUT/QOUT and

I_OFFSET/Q_OFFSET are shown in Fig. 4 but would not be

used in the normal application

In test mode, these offset controls are disabled and the offsets

are controlled using on-chip feedback. The loop filter for this

feedback uses external 10nF capacitors on pins I_OC_TEST/B

and Q_OC_TEST/B as shown in Fig. 4.

I/O

I

I

I

I

I

I

I

I

I

I

O

O

P

P

O

O

I

I

I

P

I

I

I

I

I

I

Description

Q channel offset control in test mode

Q channel offset control in test mode (balanced)

Q channel CDMA/FM input.

Q channel CDMA/FM input (balanced)

Q channel offset control

Q channel offset control (high gain mode)

Test mode signal input for tuning operation

Precision resistor for current definition (18k)

I filter tuning control

Q filter tuning control

Q channel gain adjust voltage, VGC

Q channel CDMA/FM output

Q channel CDMA/FM output (balanced)

Supply

Ground

I channel CDMA (balanced)

I channel CDMA

Reference voltage decouple

Mode control (see Table 2)

Mode control (see Table 2)

Mode control (see Table 2)

Ground (substrate)

I channel offset control (high gain mode)

I channel offset control

I channel CDMA (balanced)

I channel CDMA

I channel offset control in test mode (balanced)

I channel offset control in test mode

Name

Q_OC_TEST

Q_OC_TESTB

QIN

QINB

Q_OFFSET

Q_OFFSETB

RTUNE

ITUNE

QTUNE

QBAL

QOUT

QOUTB

IOUTB

IOUT

ENTEST

ENABLE

MODE_CDMA

I_OFFSETB

I_OFFSET

IINB

IIN

I_OC_TESTB

I_OC_TEST

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Table 1 Pin descriptions