MT8976AP datasheet(13/26 Pages) MITEL

13 / 26 page

ISO-CMOS

MT8976

4-41

Received Signalling Bits

The A, B, C and D signalling bits are output from the

device in the 24 Per Channel Status Words. Their

location in the serial steam output at CSTo is shown

in Figure 6 and the bit positions are shown in Table

11. The internal debouncing of the signalling bits can

be turned on or off by Master Control Word 1. In ESF

mode, A, B, C and D bits are valid. Even though the

signalling bits are only received once every six

frames the device stores the information so that it is

available on the ST-BUS every frame. The ST-BUS

will always contain the most recent signalling bits.

The

state

the

signalling

bits

frozen

synchronization is lost.

In D3/D4 mode, only the A and B bits are valid. The

state of the signalling bits is frozen when terminal

frame synchronization is lost. The freeze is disabled

when

the

device

regains

terminal

frame

synchronization. The signalling bits may go through a

random transition stage until the device attains

multiframe synchronization.

Clock and Framing Signals

The MT8976 requires one 2.048 MHz clock (C2i) and

an 8 kHz framing signal for the ST-BUS side. Figure

12 illustrates the relationship between the two

signals. The framing signal is used to delimit

individual 32 channel ST-BUS frames.

The DS1 side requires two clocks. A 1.544 MHz

clock used for transmit (C1.5i), and a 1.544 MHz

clock extracted from the DS1 line signal and applied

at E1.5i pin to clock in the received data.

The C2i and C1.5i clock must be phase-locked

together. There must be 193 clock cycles of C1.5i for

every 256 clock cycles of C2i. At the slave end of the

link, the C2i and C1.5i must be phase locked to the

extracted E1.5i clock.

The clock applied at E1.5i is internally divided down

by 193 and aligned with the DS1 frame. The resulting

8 kHz clock is output at the E8Ko pin. This signal

can be used as a reference for phase locking the C2i

and C1.5i clocks to the extracted 1.544 MHz clock.

DS1 Line Interface

Transmit Interface

The interface to the DS1 line is

made up of two

unipolar outputs, TxA and TxB, which can be used to

drive a bipolar transmitter circuit. The output signal

on TxA and TxB corresponds to the positive and

negative bipolar pulses required for the Alternate

Mark Inversion signal on the T1 line. The relationship

between the signal output at TxA and TxB and the

AMI signal is illustrated in Figure 5. For transmission

over twisted pair wire, the AMI signal has to be

equalized and transformer coupled to the line.

Receiver Interface

The receiver circuitry is made up of three pins RxA,

RxB and RxD. The bipolar alternate mark inversion

signal from the DS-1 line should be converted into a

unipolar split phase format. The resulting signals

are clocked into the device at RxA and RxB. The

signals are also NANDED together and input at RxD.

In special applications where the detection of bipolar

violations is not required, it is possible to clock NRZ

data

directly into RxD. In this case,

the RxA and

RxB pins should be tied high.

Data is clocked into RxA,

RxB and RxD with the

falling edge of the E1.5i clock. This clock signal is

extracted from the received data. The relationship

between the received signals and the extracted clock

is shown in Figure 4.

Elastic Buffer

The MT8976 has a two frame elastic buffer which

absorbs jitter in the received DS1 signal. The buffer

is also used in the rate conversion between the 1.544

Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS data

rate.

The received data is written into the elastic buffer

with the extracted 1.544 MHz clock. The data is read

out of the buffer on the ST-BUS side with the system

2.048 MHz clock. The maximum delay through the

buffer is 1.3 ST-BUS frames (i.e., 42 ST-BUS

channels). The minimum delay required to avoid bus

contention in the buffer memory is two ST-BUS

channels.

Under normal operating conditions, the system C2i

clock is phase locked to the extracted E1.5i clock

using external circuitry. If the two clocks are not

phase-locked, then the rate at which the data is

being written into the device on the DS1 side may

differ from the rate at which it is being read out on the

ST-BUS side. The buffer circuit will perform a

controlled slip if the throughput delay conditions

described above are violated. For example, if the

data on the DS1 side is being written in at a rate

slower than what it is being read out on the ST-BUS

side, the delay between the received DS1 write

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