ISO-CMOS

MT8976

4-35

Table 1. Master Control Word 1 (Channel 15, CSTi0)

Bit

Name

Description

7

Debounce

When set the received A, B, C and D signalling bits are reported directly in the per channel

status words output at CSTo. When clear, the signalling bits are debounced for 6 to 9 ms

before they are placed on CSTo.

6

TSPZCS

Transparent Zero Code Suppression. When this bit is set, no zero code suppression is

implemented.

5

B8ZS

Binary Eight Zero Suppression. When this bit is set, B8ZS zero code suppression is

enabled. When clear, bit 7 in data channels containing all zeros is forced high before being

transmitted on the DS1 side. This bit is inactive if the TSPZCS bit is set.

4

8KHSel

8 kHz Output Select. When set, the E8Ko pin is held high. When clear, the E8Ko

generates an 8 kHz output derived from the E1.5i or C1.5 clock (see Pin Description for

E8Ko).

3

XCtl

External Control Pin. When set, the XCtl pin is held high. When clear, XCtl is held low.

2

ESFYLW

ESF Yellow Alarm. Valid only in ESF mode. When set, a sequence of eight 1’s followed

by eight 0’s is sent in the FDL bit positions. When clear, the FDL bit contains data input at

the TxFDL pin.

1

Robbed bit

When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When

frame is enabled.

0

YLALR

Yellow Alarm. When set, bit 2 of all DS1 channels is set low. When clear, bit 2 operates

normally.

to the CRC received in the next multiframe. The

device will not declare itself to be in synchronization

unless a valid framing pattern in the S-bit is detected

and a correct CRC is received. The CRC check in

this case provides protection against false framing.

The CRC check can be turned off by setting bit 1 in

Master Control Word 2.

The device can be forced to resynchronize itself. If

Bit 3 in Master Control Word 2 is set for one frame

and then subsequently reset, the device will start to

search for a new frame position. The decision to

reframe is made by the user’s system processor on

the basis of the status conditions detected in the

received master status words. This may include

consideration of the number of errors in the received

CRC

in

conjunction with

an indication

of the

presence of a mimic. When the device attains

synchronization the mimic bit in Master Status Word

1 is set if the device found another possible

candidate when it was searching for the framing

pattern.

Note that the device will resynchronize automatically

FPS) exceed the threshold set with bit 0 in Master

Control Word 2.

Standard D3/D4 framing is enabled when bit 4 of

Master Control Word 2 is reset (logic 0).

In this

mode the device searches for and inserts the

framing pattern shown in Table 4. This mode only

supports AB bit signalling, and does not contain a

CRC check.

The CRC/MIMIC bit in Master Control Word 2, when

set high, allows the device to synchronize in the

presence of a mimic. If this bit is reset, the device will

not synchronize in the presence of a mimic (Also,

refer to section on Framing algorithm).

In the D3/D4 mode the device can also be made

compatible with SLC-96 by setting bit two of Master

Control Word 2. This allows the user to insert and

extract the signalling framing pattern on the DS1 bit

stream using the FDL input and output pins. The

user must format this 4 kbits of information externally

to meet all of the requirements of the SLC-96

specification (see Table 5). The device multiplexes

and demultiplexes this information into the proper

position. This mode of operation can also be used for

any other application that uses all or part of the

signalling framing pattern. As long as the serial

stream clocked into the TxFDL contains two proper

sets of consecutive synchronization bits (as shown

in Table 5 for frames 1 to 24), the device will be able

to insert and extract the A, B signalling bits.

The

TxSF pin should be held high in this mode.

Superframe boundaries cannot be defined by a

pulse on this input. The RxSF output functions

normally and indicates the superframe boundaries

received bit position.

Zero Code Suppression

The combination of bits 5 and 6 in Master Control

Word 1 allow one of three zero code suppression