ISO-CMOS

MT8981D

2-27

† Timing is over recommended temperature & power supply voltages

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.

NB: Frame Pulse is repeated every 512 cycles of C4i.

Figure 12 - Frame Alignment

Figure 13 - Clock Timing

Characteristics

Sym

Min

Max

Units

Test Conditions

1

I

N

P

U

T

S

Clock Period*

220

244

300

ns

2

Clock Width High

95

122

150

ns

3

Clock Width Low

110

122

150

ns

4

Clock Transition Time

20

ns

5

Frame Pulse SetupTime

20

200

ns

6

Frame Pulse Hold Time

0.020

50

µs

7

Frame Pulse Width

244

ns

C4i

F0i

2.0V

0.8V

2.0V

0.8V

C4i

F0i

BIT

CELLS

Channel 31

Bit o

Channel 0

Bit 7