CMOS

MT9085

2-141

† Timing is over recommended temperature & power supply voltages

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 17 - Serial Input and Output Timing in 4 Mbit/s Mode (2/4S=1)

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Serial Input Setup Time

0ns

2

Serial Input Hold Time

24

ns

3

Serial Output Delay

Active to Active

High Impedance to Active

Active to High Impedance

47

47

44

ns

ns

ns

C4i

C16i

S0i-S7i

(CKD=0)

S0i-S7i

(CKD=1)

S0o-S7o

(CKD=0)

S0o-S7o

(CKD=1)

Note:

1)

The phase relationship of C4i and C16i depends on the user’s timing source (see Fig. 13 for device related contstraints).

Measurements for outputs are referenced to/from a low voltage of 0.4V to a high voltage of 2.4V

Serial Bit Cell

2)

Timing measurements for inputs are referenced to/from a low voltage of 0.8V and a high voltage of 2.0V.