MT9085AP datasheet(6/20 Pages) MITEL

6 / 20 page

MT9085 CMOS

2-130

Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1)

C16i

CKD=0

Serial

Output

S0-S31

Parallel

Input

MCB=0

Parallel

Input

MCB=1

CKD=1

Serial

Output

S0-S31

Parallel

Input

MCB=0

Parallel

Input

MCB=1

Ch. 31, Bit 0

Ch. 1, Bit 7

C1S1

C1S2

C1S3

C1S0

C0S31

C1S1

C1S2

C1S3

C1S0

C0S31

C2S0

C1S1

C1S2

C1S0

C1S1

C1S2

C1S0

C0S31

C2S0

C2S1

Frame Boundary established by F0i

64 Cycles

Notes:

CXSY - on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X.

Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. CXSY written below the arrow indicates the

serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C1S1 will enable or disable the

serial output drivers for stream 1 during channel 1.

C1S3

C0S31

Ch. 0, Bit 7

C2S1

C1S1

Ch. 31, Bit 0

C1S4

C1S2

C1S3

Ch. 0, Bit 7

C1S1

C1S4

C1S2

C1S3

C1S1

C1S4

C1S2

C1S3

C2S1

C1S1

C1S2

C1S3

C1S4

C2S1

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