MT9126AS datasheet(5/22 Pages) MITEL

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Preliminary Information

MT9126

8-37

Functional Description

The Quad-channel ADPCM Transcoder is a low

power, CMOS device capable of four encode and

four decode operations per frame. Four 64 kbit/s

channels (PCM octets) are compressed into four 32,

24 or 16 kbit/s ADPCM channels (ADPCM words),

and four 32, 24 or 16 kbit/s ADPCM channels

(ADPCM words) are expanded into four 64 kbit/s

PCM

channels

(PCM

octets).

The

ADPCM

transcoding algorithm utilized conforms to ITU-T

recommendation G.726 (excluding 40 kb/s), and

ANSI T1.303 - 1989. Switching on-the-fly between

32 and 24 kbit/s transcoding is possible by toggling

the appropriate mode select pins (supports T1

robbed-bit signalling).

All functions supported by the device are pin

selectable. The four encode functions comprise a

common group controlled via Mode Select pins MS1,

MS2 and MS3. Similarily, the four decode functions

form a second group commonly controlled via Mode

Select pins MS4, MS5 and MS6. All other pin

controls are common to the entire transcoder.

The device requires 25 mWatts (MCLK= 4.096 MHz)

typically for four channel transcode operation. A

minimum master clock frequency of 4.096 MHz is

required for the circuit to complete four encode

channels and four decode channels per frame. For

SSI operation a master clock frequency greater than

4.096 MHz and asynchronous, relative to the 8 kHz

frame, is allowed.

The PCM and ADPCM serial busses support both

ST-BUS and Synchronous Serial Interface (SSI)

operation. This allows serial data clock rates from

128 kHz to 4096 kHz, as well as compatibility with

Mitel’s standard Serial Telecom BUS (ST-BUS). For

ST-BUS operation, on chip channel counters provide

channel enable outputs as well as a 2048 kHz bit

clock output which may be used by down-stream

devices utilizing the SSI bus interface.

Linear coded PCM is also supported. In this mode

the

encoders

compress,

four

14-bit,

two’s

complement

(S,S,S,12,...,1,0),

uniform

PCM

channels into four 4, 3 or 2 bit ADPCM channels.

Similarly, the decoder expands four 4, 3 or 2 bit

ADPCM channels into four 16-bit, two’s complement

(S,14,...,1,0), uniform PCM channels. The data rate

for both ST-BUS and SSI operation in this mode is

2048 kbit/s.

Serial (AD)PCM Data I/O

Serial data transfer to/from the Quad ADPCM

transcoder is provided through one ADPCM and two

PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1,

PCMi2, PCMo2). Data is transferred through these

ports

according

either

ST-BUS

SSI

requirements. The device determines the mode of

operation by monitoring the signal applied to the F0i

pin. When a valid ST-BUS frame pulse (244nSec low

going pulse) is applied to the F0i pin the transcoder

will assume

ST-BUS

operation.

F0i

tied

continuously to VSS the transcoder will assume SSI

operation. Pin functionality in each of these modes is

described in the following sub-sections.

ST-BUS Mode

During ST-BUS operation the C2o, EN1, EN2 and

F0od outputs become active and all serial timing is

derived from the MCLK (C4) and F0i inputs while the

BCLK input is tied to VSS. (See Figures 7, 8 & 9.)

Basic Rate “D” and “C” Channels

In ST-BUS mode, when ENB1 is brought low,

transparent transport of the ST-BUS "Basic Rate D-

and C-channels" is supported through the PCMi1

and PCMo1 pins. This allows a microprocessor

controlled device, connected to the PCMi/o1 pins, to

access the "D" and "C" channels of a transmission

device connected to the ADPCMi/o pins. When

ENB1 is brought high, the “D” and “C” channel

outputs are tristated. Basic Rate “D” and “C”

channels are not supported in LINEAR mode.(See

Figure 7.)

SSI Mode

During SSI operation the BCLK, ENB1 and ENB2/

F0od inputs become active. The C2o, EN1, and EN2

outputs are forced to a high-impedance state except

during LINEAR operation during which the EN1

output remains active. (See Figures 4, 5 & 6.)

The SSI port is a serial data interface, including data

input and data output pins, a variable rate bit clock

input and two input strobes providing enables for

data transfers. There are three SSI I/O ports on the

Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2

PCM port, and the ADPCMi/o port. The two PCM

ports may transport 8-bit companded PCM or 16-bit

linear PCM. The alignment of the channels is

determined by the two input strobe signals ENB1

and ENB2/F0od. The bit clock (BCLK) and input

strobes (ENB1 and ENB2/F0od) are common for all

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