MT9126AS datasheet(7/22 Pages) MITEL

7 / 22 page

Preliminary Information

MT9126

8-39

mode. Similarily, the four 2-bit ADPCM words on

ADPCMi are transparently bypassed, with a two

frame delay, to PCMo1 and PCMo2 during the ENB1

or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6

& 9.)

When SEL is set to 1, the same bypass occurs as

described when SEL = 0 except that the ENB2 or B2

timeslots are utilized.

LINEAR, FORMAT and A/

µ pins are ignored in

bypass mode.

PCM BYPASS

When SEL is set to 0, the B1 and B2 PCM channels

on PCMi1 are transparently passed, with a two-

frame delay, to the same channels on the ADPCMo.

Simiarily, the two 8-bit words which are on ADPCMi

are transparently passed, with a two-frame delay, to

channels B1 and B2 of PCMo1 while PCMo2 is set

to a high-impedance state.(See Figures 6 & 9.)

When SEL is set to 1, the B3 and B4 channels on

PCMi2 are transparently passed, with a two frame

delay, to the same channels on ADPCMo. Similarily,

the two 8-bit words which are on ADPCMi are

transparently passed, with a two-frame delay, to

channels B3 and B4 of PCMo2. In this case PCMo1

is always high-impedance if ENB1 = 0. If ENB1 = 1

during ST-BUS operation then the D and C channels

are active on PCMo1.

LINEAR, FORMAT and A/

µ pins are ignored in

bypass mode.

Algorithm Reset Mode

While an algorithmic reset is asserted the device will

incrementally converge its internal variables to the

'Optional reset values' stated in G.726. Algorithmic

reset requires that the master clock (MCLK) and

frame pulse (ENB1/2 or F0i) remain active and that

the reset condition be valid for at least four frames.

Note that this is not a power down mode; see

PWRDN for this function.

ADPCMo & PCMo1/2 Disable

When the encoders are programmed for ADPCMo

disable (MS1 to MS3 set to 1) the ADPCMo output is

set to a high impedance state and the internal

encode

function

remains

active.

Therefore

convergence is maintained. The decode processing

function and data I/O remain active.

When the decoders are programmed for PCMo1/2

disable (MS4 to MS6 set to 1) the PCMo1/2 outputs

are high impedance during the B Channel timeslots

and also, during ST-BUS operation, the D and C

channel timeslots according to the state of ENB1.

Therefore convergence is maintained. The encode

processing function and data I/O remain active.

Whenever any combination of the encoders or

decoders are set to the disable mode the following

outputs remain active. A) ST-BUS mode: ENB2/

F0od, EN1, EN2 and C2o. Also the “D” and “C”

channels from PCMo1 and ADPCMo remain active if

ENB1 is set to 0. If ENB1 is brought high then

PCMo1 and ADPCMo are fully tri-stated. B) SSI

mode: When used in the 16-bit linear mode, only the

EN1 output remains active. For complete chip power

down see PWRDN.

Other Pin Controls

16 Bit Linear PCM

Setting the LINEAR pin to logic one causes the

device to change to 16-bit linear (uniform) PCM

transmission on the PCMi/o1 and PCMi/o2 ports.

The data rate for both ST-BUS and SSI operation in

this mode is 2048 kbit/s and all decode and encode

functions are affected by this pin. In SSI mode, the

input channel strobes ENB1 and ENB2/F0od remain

active for 8 cycles of BCLK for an ADPCM transfer.

The EN1 output is high for one BCLK period at the

end of the frame (i.e., during the 256th BCLK period).

In ST-BUS mode, the output strobes EN1 and ENB2/

F0od are adjusted to accommodate the required

PCM I/O streams. The EN1 output becomes a single

bit high true pulse during the last clock period of the

frame (i.e., the 256th bit period) while ENB2/F0od

becomes a delayed, low true frame-pulse (F0od)

output occuring during the 64th bit period after the

EN1 rising edge.

Linear PCM on PCMi1 and PCMi2, are received as

14-bit, two’s complement data with three bits of sign

extension in the most significant positions (i.e.,

S,S,S,12,...1,0) for a total of 16 bits. The linear PCM

data transmitted from PCMo1 and PCmo2 are 16-bit,

two’s complement data with one sign bit in the most

significant position (i.e., S,14,13,...1,0)

32 and 24 kbit/s ADPCM mode

In 32 kbit/s and 24 kbit/s linear mode, the 16-bit

uniform PCM dual-octets of the B1, B2, B3 and B4

channels (from PCMi1 and PCMi2) are compressed

into four 4-bit words on ADPCMo. The four 4-bit

ADPCM words of the B1, B2, B3 and B4 channels

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