MT9126AS datasheet(6/22 Pages) MITEL

6 / 22 page

MT9126

Preliminary Information

8-38

three of the serial I/O ports. BCLK can be any

frequency

between

128

kHz

and

4096

kHz

synchronized to the input strobes. BCLK may be

discontinuous outside of the strobe boundaries

except when LINEAR=1. In LINEAR mode, BCLK

must be 2048 kHz and continuous for 64 cycles after

the ENB1 rising edge and for the duration of ENB2/

F0od.

Mode Select Operation (MS1, MS2, MS3,

MS4, MS5, MS6)

Mode Select pins MS1, MS2 and MS3 program

different bit rate ADPCM coding, bypass, algorithmic

reset and disable modes for all four encoder

functions simultaneously. When 24 kbit/s ADPCM

mode is selected bit 4 is unused while in 16 kb/s

ADPCM mode all ADPCM channels are packed

contiguously into one 8-bit octet. Mode Select pins

MS4, MS5 and MS6 operate in the same manner for

the four decode functions. The mode selects must be

set up according to the timing constraints illustrated

in Figures 16 and 17.

32 kbit/s ADPCM Mode

In 32 kbit/s ADPCM mode, the 8-bit PCM octets of

the B1, B2, B3 and B4 channels (PCMi1 and PCMi2)

are compressed into four 4-bit ADPCM words on

ADPCMo. Conversely, the 4-bit ADPCM words of the

B1, B2, B3 and B4 channels from ADPCMi

are

expanded into four 8-bit PCM octets on PCMo1 and

PCMo2. The 8-bit PCM octets (A-Law or

µ-Law) are

transferred most significant bit first starting with b7

and ending with b0. ADPCM words are transferred

most significant bit first starting with I1 and ending

with I4 (See Figures 4 & 7). Reference ITU-T G.726

for I-bit definitions.

24 kbit/s ADPCM Mode

In 24 kbit/s mode PCM octets are transcoded into 3-

bit words rather than the 4-bit words utilized in 32

kbit/s ADPCM. This is useful in situations where

lower bandwidth transmission is required. Dynamic

operation of the mode select control pins will allow

switching from 32 kbit/s mode to 24 kbit/s mode on a

frame by frame basis. The 8 bit PCM octets (A-Law

µ-Law) are transferred most significant bit first

starting with b7 and ending with b0. ADPCM words

are transferred most significant bit first starting with

I1 and ending with I3 (I4 becomes don’t care). (See

Figures 4 & 7.)

16 kbit/s ADPCM Mode

When SEL is set to 0, the 8-bit PCM octets of the B1,

B2, B3 and B4 channels (PCMi1 and PCMi2) are

compressed

into

four

2-bit

ADPCM

words

ADPCMo during the ENB1 timeslot in SSI mode and

during the B1 timeslot in ST-BUS mode. Similarily,

the four 2-bit ADPCM words on ADPCMi are

expanded into four 8-bit PCM octets (on PCMo1 and

PCMo2) during the ENB1/B1 timeslot. (See Figures 4

& 7.)

When SEL is set to 1, The same conversion takes

place as described when SEL = 0 except that the

ENB2/B2 timeslots are utilized.

A-Law or

µ-Law 8-bit PCM are received and

transmitted most significant bit first starting with b7

and

ending

with

b0.

ADPCM

data

are

most

significant bit first starting with I1 and ending with I2.

ADPCM BYPASS (32 and 24 kbit/s)

In ADPCM bypass mode the B1 and B2 channel

ADPCM words are bypassed (with a two-frame

delay) to/from the ADPCM port and placed into the

most significant nibbles of the PCM1/2 port octets.

Note that the SEL pin performs no function for these

two modes (See Figures 6 & 9). LINEAR, FORMAT

and A/

µ pins are ignored in bypass mode.

In 32 kb/s ADPCM bypass mode, Bits 1 to 4 of the

B1, B2, B3 and B4 channels from PCMi1 and PCMi2

are transparently passed, with a two frame delay, to

the same channels on ADPCMo. In the same

manner, the B1, B2, B3 and B4 channels from

ADPCMi are transparently passed, with a two frame

delay, to the same channels on PCMo1 and PCMo2

pins. Bits 5 to 8 are don’t care. This feature allows

two

voice

terminals,

which

utilize

ADPCM

transcoding, to communicate through a system

without

incurring

unnecessary

transcode

conversions. This arrangement allows byte-wide or

nibble-wide transport through a switching matrix.

24 kb/s ADPCM bypass mode is the same as 32 kb/s

mode bypass excepting that only bits 1 to 3 are

bypassed and bits 4 to 8 are don’t care.

ADPCM BYPASS (16 kbit/s)

When SEL is set to 0, only bits 1 and 2 of the B1, B2,

B3 and B4 PCM octets (on PCMi1 and PCMi2) are

bypassed, with a two frame delay, to the same

channels on ADPCMo during the ENB1 timeslot in

SSI mode and during the B1 timeslot in ST-BUS

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