TMP175-Q1, TMP75-Q1

SBOS759 – NOVEMBER 2015

www.ti.com

6.6 Timing Requirements

see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information

(1)

HIGH-SPEED

FAST MODE

MODE

UNIT

MIN

MAX

MIN

MAX

SCL operating frequency

V+

0.001

0.4

0.001

2.38

MHz

Bus-free time between STOP and START

1300

160

ns

condition

Hold time after repeated START condition.

600

160

ns

After this period, the first clock is generated.

See the Timing Diagrams section

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

4

900

4

120

ns

Data setup time

100

10

ns

SCL clock low period

V+ , see the Timing Diagrams section

1300

280

ns

SCL clock high period

See the Timing Diagrams section

600

60

ns

Data fall time

See the Timing Diagrams section

300

150

ns

See the Two-Wire Timing Diagrams section

300

40

ns

Clock rise time

SCLK

≤ 100 kHz, see the Timing Diagrams

1000

ns

section

Clock fall time

See the Two-Wire Timing Diagrams section

300

40

ns

(1)

Values are based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and are not

production tested.

6

Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: TMP175-Q1 TMP75-Q1