DS4878 Issue 4.0 October 1999

SP5769

Preliminary information

Figure 1 SP5769 block diagram

Ordering Information

SP5769A/KG/MP1S (Tubes)

SP5769A/KG/MP1T (Tape and Reel)

SP5769A/KG/QP1S (Tubes)

SP5769A/KG/QP1T (Tape and Reel)

Features

Frequencies up to 4 MHz

Cat.1 (Normal ESD handling procedures should be

observed)

Applications

The SP5769 is a single chip frequency synthesiser

designed for tuning systems up to 3GHz. The RF

preamplifier interfaces direct with the RF programmable

divider, which is of MN1A construction so giving a step

Absolute Maximum Ratings

RF differential input voltage

All I/O port DC offsets

SDA and SCL DC offset

Storage temperature

Junction temperature

MP16 thermal resistance

Chip to ambient,

Chip to case,

0·3V to 17V

2·5Vp-p

20·3 to 6V

255

°C to 1125°C

1150

°C

80

°C/W

20

°C/W

size equal to the loop comparison frequency and no

prescaler phase noise degradation over the full RF

operating range. The comparison frequency is obtained

either from an on-chip crystal controlled oscillator, or from

COMP output providing a reference for a second frequency

4-BIT LATCH AND

PORT INTERFACE

4-BIT

COUNT

11-BIT

COUNT

15-BIT LATCH

REFERENCE

DIVIDER

REF/COMP

CRYSTAL CAP

CRYSTAL

CHARGE PUMP

DRIVE

TRANSCEIVER

ADDRESS

SDA

SCL

RF

INPUT

P3

11

2

3

1

16

6

13

14

10

4

5

PUMP

2 BIT

4 BIT

2 BIT

3 BIT

78

9

P2

P1

P0

CP TEST

MODE SET

LOCK

ENABLE/

SELECT