4

SP5769

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

R3

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

R2

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

R1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R0

Division ratio

byte data is retained. To facilitate smooth fine tuning, the

frequency data bytes are only accepted by the device after

all 15 bits of frequency data have been received, or after

the generation of a STOP condition.

Read mode

When the device is in read mode, the status byte read

from the device takes the form shown in Table 3.

Bit 1 (POR) is the power-on reset indicator, and this is set

below 3V (at 25

°C ), e.g. when the device is initially turned

on. The POR is reset to ‘0’ when the read sequence is

terminated by a STOP command. When POR is set high

this indicates the programmed information may be

corrupted and the device reset to power up condition.

Bit 2 (FL) indicates whether the device is phase locked, a

logic’1’is present if the device is locked, and a logic ‘0’ if it

is not.

Programable features

above.

described above.

be programmed by bits C1 and C0 within data byte 5,

as defined in Table 6.

T2 = 1, with selected test modes as defined by bits T1

and T0 as described in Table 5. Clock input on crystal

and RF input pins are required to invoke FL test modes.

can be switched to the REF/COMP output, function as

defined in Table 7. RE and RS default to logic’1’during

device power up, thus enabling the comparison

Write mode

With reference to Table 2, bytes 2 and 3 contain frequency

reference divider ratio (see Table 1), charge pump setting

(see Table 6), REF/COMP output (see Table 7), output

ports and test modes (see Table 5).

After reception and acknowledgement of a correct address

(byte 1), the first bit of the following byte determines whether

the byte is interpreted as a byte 2 or 4, a logic ‘0’ indicating

byte 2, and a logic ‘1’ indicating byte 4. Having interpreted

this byte as either byte 2 or 4, the following data byte will

be interpreted as byte 3 or 5 respectively. Having received

two complete data bytes, additional data bytes can be

entered, where byte interpretation follows the same

procedure, without re-addressing the device. This

procedure continues until a STOP condition is received.

The STOP condition can be generated after any data byte,

if however it occurs during a byte transmission, the previous

Table 1 Reference division ratios

2

4

8

16

32

64

128

256

24

5

10

20

40

80

160

320

Address

Programmable divider

Programmable divider

Control data

Control data

1

0

1

C1

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

1

T2

C0

0

T1

RE

0

T0

RS

0

R3

P3

MA1

R2

P2

MA0

R1

P1

0

R0

P0

A

A

A

A

A

Table 2 Write data format (MSB transmitted first)

MSB

LSB

A

Acknowledge bit

MA1, MA0

Variable address bits (see Table 4)

Programmable division ratio control bits

R3-R0

Reference division ratio select (see Table 1)

C1, C0

Charge pump current select (see Table 6)

RE

Reference oscillator output enable

RS

REF/COMP output select when RE=1 (see Table 7)

T2-T0

Test mode control bits (see Table 5)

P3-P0

P3, P2, P1 and P0 port output states