VP5313 datasheet(10/19 Pages) MITEL

10 / 19 page

VP5313/VP5513

default (power up) the TRS slave mode is selected. All internal

timing signals are derived from the input clock, (PXCK) this

must be derived from a crystal controlled oscillator. Input pixel

data is latched on the rising edge of the PXCK clock.

The video timing generator produces the internal blanking and

burst gate pulses, together with the composite sync output

signal.

H&V slave mode is enabled by setting the SYNCM1-0 bits

in the MODE register to 01. In this mode the position of the

video syncs is derived from the HS and VS inputs. These HS

and VS pins are automatically configured as inputs.

Video Timing - Master sync mode

When SYNCM1-0 of the MODE register are 10, the

VP5313/VP5513 operates in a MASTER sync mode, all

REC656 timing reference codes are ignored with VS, HS and

FC0-2 outputs providing synchronisation signals to an

external (MPEG) device. The PXCK signal is, however, still

used to generate all internal clocks. In master mode the

direction setting of bits 4 - 0 of the IICEXCTL register are

ignored.

VS is the start of the field sync datum in the middle of the

equalisation pulses. HS is the line sync which is used by the

preceding MPEG2 decoder to define when to output digital

video data to the VP5313/VP5513. The position of the falling

edge of HS relative to the first data Cb0, can be programmed

in HSOFFM-L registers, see figure 5.

Genlock using REFSQ input

The VP5313/VP5513 can be Genlocked to another video

source by setting GENLKEN high (in GCR register) and

feeding a phase coherent sub carrier frequency signal into

REFSQ. Under normal circumstances, REFSQ will be the

same frequency as the sub carrier; however if FSC4SEL is set

high (in GCR register), a 4 x sub carrier frequency signal may

be input to REFSQ. In this case, the Genlock circuit can be

reset to the required phase of REFSQ, by supplying a pulse

to SCSYNC. The frequency of SCSYNC can be at the sub

carrier frequency, once per line or once per field could be

adequate, depending on the application. When GENLKEN is

set high, the direction setting of bit 5 of the IICEXCTL register

is ignored.

PALID input

When using PAL and Genlock mode; the VP5313/VP5513

requires a PAL phase identification signal, to define the

correct phase on every line. This is supplied to PALID input,

High = -135

° and low = +135°. The signal is asynchronous,

and should by changed before the sub carrier burst signal.

PALID input is enabled by setting PALIDEN high (in GCR

bit 7 of the IICEXCTL register is ignored.

Line 21 coding

Two bytes of data are coded on the line 21 of each field,

see figure 8. In the NTSC Closed Caption service, the default

state is to code on line 21 of field one only. An additional

service can also be provided using line 21 (284) of the second

field. The data is coded as NRZ with odd parity, after a clock

run-in and framing code. The clock run-in frequency =

0.5034965MHz which is related to the nominal line period, D

= H / 32.

D = 63.55555556 / 32

µs

Two data bytes per field are loaded via I2C bus registers

CCREG1-4. Each field can be independently enabled by

programming the enable bits in the control register (CC_CTL).

The data is cleared to zero in the

Closed Caption shift

registers after it has been encoded by the VP5313/VP5513.

Two status bit are provided (in CC_CTL), which are set high

when data is written to the registers and set low when the data

has been encoded on the Luma signal. The data is cleared to

zero in the Closed Caption shift registers after it has been

encoded by the VP5313/VP5513. The next data bytes must

be written to the registers when the status bit goes high,

otherwise the Closed Caption data output will contain Null

characters. If a transmission slot is missed (ie. no data

received) the encoder will send Null characters. Null

characters are invisible to a closed caption reciever. The MSB

(bit 7) is the parity bit and is automatically added by the

encoder.

Teletext

The Teletext function within the VP5313/VP5513 co-

ordinates the insertion of teletext serial data into the

luminance data stream and subsequently the composite video

data stream.

The serial data is filtered prior to insertion to minimise the

high frequency components and to reduce the jitter inherent in

the digital data stream.

The lines in which teletext data are inserted are individually

programmable for both even and odd fields. The insertion of

teletext data will only be enabled if the format of the composite

video is configured to be PAL-B,G,H,I,N and the teletext

enable bit TTXEN is asserted.

For test purposes, the teletext function incorporates

control logic to generate a serial clock cracker pattern in place

of the normal teletext data. This test pattern is enabled when

the TTX_PAT bit is asserted. There is no row coding used so

it will not display on a TV.

The VP5313/VP5513 teletext interface comprises of a

teletext request output, TTX_REQ, and a serial data input,

TTX_DATA.

To ensure that the composite video timing requirements

are satisfied, the serial data must be received at a specific

point in time during lines containing teletext data. The teletext

request output, TTX_REQ, will be asserted to indicate when

data must be applied to TTX_DATA, which must be generated

synchronous to the rising edges of PXCK. The TTX_REQ may

be advanced in multiples of PXCK, to compensate for the

latency within the source device, by writing to the TTXDD

The serial teletext data which is applied to the TTX_DATA

input must obey the sequence defined below.

The teletext bit rate is defined to be 6.9375 MHz, which

equates to 444 times the PAL line frequency (15.625 kHz). It

is clear that for a 27 MHz system clock, a constant bit period

cannot be achieved.

VP5313 Datasheet(PDF) 10 Page - Mitel Networks Corporation

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