ISO5852S datasheet(18/37 Pages) TI

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ISO5852S

SLLSEQ0A – AUGUST 2015 – REVISED SEPTEMBER 2015

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Feature Description (continued)

9.3.6 High Voltage Feature Description

9.3.6.1 Package Insulation and Safety-Related Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

L(I01)

Minimum air gap (clearance)

Shortest terminal-to-terminal distance through air

Shortest terminal-to-terminal distance across the package

L(I02)(1)

Minimum external tracking (creepage)

surface

DIN EN 60112 (VDE 0303-11);

Tracking resistance (comparative

CTI

IEC 60112; Material Group I according to IEC 60664-1;

600

tracking index)

UL 746A

(1)

Per JEDEC package dimensions.

NOTE

Creepage and clearance requirements should be applied according to the specific

equipment isolation standards of an application. Care should be taken to maintain the

creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to

help increase these specifications.

9.3.6.2 Insulation Characteristics

PARAMETER

TEST CONDITIONS

SPECIFICATION

UNIT

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

μm

1500

VRMS

VIOWM

Maximum isolation working voltage

Time dependent dielectric breakdown (TDDB) Test

2121

VDC

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

VIORM

Maximum repetitive peak isolation voltage

2121

Method A, After Input/Output safety test subgroup 2/3,

VPR = 1.2 x VIORM, t = 10 sec,

2545

Partial discharge < 5 pC

Method A, After environmental tests subgroup 1,

VPR

Input to output test voltage

VPR = 1.6 × VIORM, t = 10 sec (qualification)

3393

Partial discharge < 5 pC

VPK

Method B1, 100% Production test,

VPR = 1.875 × VIORM, t = 1 sec

3976

Partial discharge < 5 pC

VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100%

VIOTM

Maximum Transient isolation voltage

8000

production)

Test method per IEC 60065, 1.2/50

μs waveform, VTEST =

VIOSM

Maximum surge isolation voltage

8000

1.6 x VIOSM = 12800 VPK (qualification)

(1)

Insulation resistance

VIO = 500 V at TS

Ω

> 109

VIO = 500 V, TA = 25°C

Ω

> 1012

RIO

Isolation resistance, input to output(2)

VIO = 500 V, 100°C ≤ TA ≤ max

Ω

> 1011

CIO

Barrier capacitance, input to output(2)

VIO = 0.4 x sin (2πft), f = 1 MHz

Pollution degree

UL 1577

VTEST = VISO, t = 60 sec (qualification),

VISO

Withstanding Isolation voltage

VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100%

5700

VRMS

production)

(1)

Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(2)

All pins on each side of the barrier tied together creating a two-terminal device

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