SM8577B datasheet(9/10 Pages) NPC

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SM8577B

NIPPON PRECISION CIRCUITS—9

Data Read

When CE is HIGH, data read mode starts from the

ﬁrst rising edge of CLK for which DATA is LOW.

Valid data is then output on DATA from the 9th

rising edge of CLK. Time and date data is loaded

into the shift register on the 8th falling edge of CLK

and then output on DATA in sync with the rising

edge of CLK, starting with the seconds’ digit LSB.

Data is loaded and shifted in the sequence second,

minute, hour, week, day, and month. The output data

is valid for the ﬁrst 60 rising edges of CLK. Output

data does not change after the 60th rising edge, even

if clock input continues.

Within the 60 cycles of valid data output, partial data

output can be obtained by taking CE LOW after the

corresponding number of cycles. For example, if

only the ‘second’ to ‘week’ data output is required,

then that data only is output if CE goes LOW after 36

clock cycles.

For continuous data reads, a wait time (tRCV) is

required before the next data cycle after CE goes

LOW.

Note that if a timer counter update operation (a 1 s

carry) occurs during a data read cycle, the data in the

shift register is not updated and, as a result, the

output data contains an error of

−1 s.

The data read cycle should be completed within

tCE ≤ 0.9 s.

Data Write

CLK

DATA

Control Bits

Year

60+n

Data Input Mode

y20

y40

y80

Second

Data Output Mode

Don't Care

Output data

not change

CLK

DATA

Control Bits

Year

60+n

Data Input Mode

y20

y40

y80

Second

Data Input Mode

Don

′t Care

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