SM8702AM

NIPPON PRECISION CIRCUITS—12

Operating Mode Summary

The state of the various external inputs and outputs in the operating modes is indicated in the following table.

CPU Clock Stop Function

In mobile mode, selected using MODE (pin 7), the CPUCLK[0:1] clock outputs can be stopped by external pin

control. The asynchronous stop signal input on CPU_STOP# is sampled internally on the rising edge of the

PCI free-running output clock (PCICLK_F).

When CPU_STOP# goes LOW, the CPU clock outputs (CPUCLK) stop after a delay of 2 to 4 clock cycles.

When CPU_STOP# goes HIGH, the CPU clock outputs start after a delay of 2 to 4 clock cycles. The actual

start and stop delay varies with the output frequency up to a maximum of 4 CPU clock cycles.

MODE

SDRAM11/

CPU_ST OP#

SDRAM10/

PCI_STO P #

CPUCLK[0:1] PCICLK[0:4]

PCICLK_F,

24MHz/48MHz,

SDRAM[0:13]

C r ystal

oscillator

VCO

(internal

signal)

1. Enab led = output functions active. Disabled = LOW -level output.

MODE = HIGH

(desktop

mode)

Enab led

(SDRAM output)

Enab led

(SDRAM output)

Enab led

Enab led

Enab led

Enab led

Enab led

Desktop mode.

Pins 17 and 18

function as outputs.

MODE = LOW

(mobile mode)

HIGH

(CPU_STOP# input)

HIGH

(PCI_STOP# input)

Enab led

Enab led

Enab led

Enab led

Enab led

Mobile mode.

Pins 17 and 18

function as inputs.

Pin 17 =

CPU_ST OP#

Pin 18 =

PCI_STO P #

HIGH

(CPU_STOP# input)

LO W

(PCI_STOP# input)

Enab led

Disabled

Enab led

Enab led

Enab led

LO W

(CPU_STOP# input)

HIGH

(PCI_STOP# input)

Disabled

Enab led

Enab led

Enab led

Enab led

LO W

(CPU_STOP# input)

LO W

(PCI_STOP# input)

Disabled

Disabled

Enab led

Enab led

Enab led

CPU_STOP#

CPUCLK

(external)

PCI_STOP#

(All "H")

PCICLK_F

(free-running)

CPUCLK

(internal)

PCICLK

(internal)