SM8750AV datasheet(4/10 Pages) NPC

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SM8750AV

NIPPON PRECISION CIRCUITS—4

Phase Difference to Voltage Converter Characteristics

VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C

Auto-adjust Characteristics

VDD = 5V ± 5%, GND = 0V, Ta = 0 to 70°C

P arameter

Condition

Rating

Unit

min

typ

m a x

RDCLK input frequency

FCG = LOW

–

58.38

7 0

MHz

FCG = HIGH

–

29.19

3 5

Phase difference to voltage converter

coefﬁcient 1

N o r mal operation, FCG = L O W

5 0

7 5

1 0 0

mV/ns

Phase difference to voltage converter

coefﬁcient 2

C o n ver ter coefﬁcient measurement mode,

FCG = L O W

2 5

37.5

5 0

mV/ns

N o r mal operation, FCG = HIGH

2 5

37.5

5 0

Phase difference to voltage converter

coefﬁcient 3

C o n ver ter coefﬁcient measurement mode,

FCG = HIGH

12.5

18.75

2 5

mV/ns

C o n ver ter coefﬁcient relative accuracy

See note.1

1. {[(conver ter coefﬁcient 2)

× 2 / (converter coefﬁcient 1)] − 1} × 100

––

±5

C o n ver ter coefﬁcient relative accuracy

See note.2

2. {[(conver ter coefﬁcient 3)

× 2 / (converter coefﬁcient 2)] − 1} × 100

––

±5

Output offset voltage

After VREF2 reference calibration

–

±25

m V

C o n ver ter voltage settling time

Time from measurement object DATA

edge to ﬁnal set value ± 0.5%

–

0.75

µ s

C o n ver ter voltage reset time

Time from STA R T signal rising edge to

ﬁnal reset value ± 1mV

––3

µ s

Output load regulation

IL = 0.5mA

–

2 0

m V

HIGH-level output voltage range

LIMIT pin voltage reference

+0.15

–

+0.45

L O W -level output voltage range

0.8

–

Output voltage droop

–

mV/µs

S TA R T-DATA setup time3

3. T = RDCLK cycle time

S TA R T signal rising edge to DATA signal

edge

–

P arameter

Condition

Rating

Unit

min

typ

m a x

Maxim um DATA edge delay adjust range

–

2 9

–

Minimu m DATA edge delay adjust range

–

12.5

–

Maxim u m RDCLK pulsewidth adjust range

FCG = LOW

–1 5–

Minimum RDCLK pulsewidth adjust range

–

Maxim u m RDCLK pulsewidth adjust range

FCG = HIGH

–2 8–

Minimum RDCLK pulsewidth adjust range

–

A uto-adjustment time

After CS = HIGH, until settling

–

m s

RCP voltage

C o n ver ter coefﬁcients set

–

HIGH-level RDATAR/RDATAF voltage

Minimu m DATA delay

–

1.92

–

L O W -level RDATAR/RDATAF voltage

Maxim um DATA delay

–

0.69

–

HIGH-level RDUTY voltage

Minimum RDCLK pulsewidth

–

1.88

–

L O W -level RDUTY voltage

Maxim u m RDCLK pulsewidth

–

0.24

–

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