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FS7140 Datasheet(PDF) 5 Page - ON Semiconductor |
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FS7140 Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 17 page ![]() FS7140, FS7145 http://onsemi.com 5 Table 4. DC ELECTRICAL SPECIFICATIONS (Note 1) Parameter Units Max Typ Min Conditions/Description Symbol CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP) Low−level output sink current IOL VO = 0.4 V −35 mA CLOCK OUTPUTS, PECL MODE (CLKN, CLKP) IPRG bias voltage VIPRG VIPRG will be clamped to this level when a resistor is connected from VDD to IPRG VDD/3 V IPRG bias current IIPRG IIPRG − (VVDD − VIPRG) / RSET 3.5 mA Sink current to IPRG current ratio 13 Tristate output current IZ −10 10 mA 1. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza- tion data are ± 3s from typical. Negative currents indicate flows out of the device. Table 5. AC TIMING SPECIFICATIONS (Note 2) Parameter Symbol Conditions/Description Min Typ Max Units OVERALL Output frequency* fo(max) CMOS outputs 0 150 MHz PECL outputs 0 300 VCO frequency* fVCO 40 400 MHz CMOS mode rise time* tr CL = 7 pF 1 ns CMOS mode fall time* tf CL = 7 pF 1 ns PECL mode rise time* tr CL = 7 pF; RL = 65 ohm 1 ns PECL mode fall time* tf CL = 7 pF; RL = 65 ohm 1 ns REFERENCE FREQUENCY INPUT (REF) Input frequency FREF 80 MHz Reference high time tREHF 3 ns Reference low time tREFL 3 ns SYNC CONTROL INPUT (SYNC) Sync high time tSYNCH For orderly CLK stop/start 3 TCLK Sync low time tSYNCL For orderly CLK stop/start 3 CLOCK OUTPUT (CLKN, CLKP) Duty cycle (CMOS mode)* Measured at 1.4 V 50 % Duty cycle (PECL mode)* Measured at zero crossings of (VCLKP − VCLKN) 50 % Jitter, long term (sy(t))* tj(LT) For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer us- ing a 500 microsecond window, using statistics gathered over 1000 samples. ps FREF/NREF > 1000 kHz 25 ps FREF/NREF ^ 500 kHz 50 ps FREF/NREF ^ 250 kHz 100 ps FREF/NREF ^ 125 kHz 190 ps FREF/NREF ^ 62.5 kHz 240 ps FREF/NREF ^ 31.5 kHz 300 ps Jitter, period (peak−peak)* tj(DP) 40 MHz < VCO frequency < 100 MHz 75 ps VCO frequency > 100 MHz 50 ps 2. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. |
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