RHYTHM R3710

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5

Parameter

Symbol

Standard Mode

Fast Mode

Units

Min

Max

Min

Max

Clock Frequency

0

100

0

400

kHz

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

4.0

−

0.6

−

msec

LOW Period of the PC_CLK Clock

4.7

−

−

−

msec

HIGH Period of the PC_CLK Clock

4.0

−

−

−

msec

Set−up time for a repeated START condition

4.7

−

−

−

msec

Data Hold Time:

for CBUS Compatible Masters

5.0

0 (Note 1)

−

3.45 (Note 2)

−

0 (Note 1)

−

0.9 (Note 2)

msec

Data set−up time

250

−

100

−

nsec

Rise time of both PC_SDA and PC_CLK signals

−

1000

(Note 4)

300

nsec

Fall time of both PC_SDA and PC_CLK signals

−

300

(Note 4)

300

nsec

Set−up time for STOP condition

4.0

−

0.6

−

nsec

Bus free time between a STOP and

START condition

4.7

−

1.3

−

msec

capacitance from 10 pF to 400 pF

−

250

250

nsec

Pulse width of spikes which must be suppressed

by the input filter

n/a

n/a

0

50

nsec

Capacitive load for each bus line

−

400

−

400

pF

1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.

This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the