| Electronic Components Datasheet Search |
|
AP3603 Datasheet(PDF) 9 Page - Asahi Kasei Microsystems |
|
|
|||||||||||||||||||||||||||||
AP3603 Datasheet(HTML) 9 Page - Asahi Kasei Microsystems |
|
9 / 18 page ![]() [AP3603] 015000004-E-02 2015/07 - 9 - 10.8 CC1 and CC2 Pin Voltage (Error Amplifier output) Clamping Function The voltage of CC pin (CC1 and CC2) which is the output of error amplifier stays around 1.2V (SS pin voltage) under the condition of normal PWM operation. The feedback response goes worse in case the voltage difference between CC pin (CC1 and CC2) and 1.2V becomes large under the abnormal condition like the output voltage beyond setting voltage. It causes the over shoot or under shoot. The AP3603 clamps the voltage of CC pin (CC1 and CC2) as below to prevent CC pin (CC1 and CC2) voltage from going out of a normal operating condition Detect condition Release condition Operation CCx pin voltage≦0.9V or FBx pin voltage≦3.6V×75% Switching command has requested or FBx pin voltage≧3.6V×85% CCx pin connects to SS pin and Error Amplifier output disconnect to CCx pin 10.9 External Synchronous Operation External synchronization is available by an input timing signal to the FSYN pin. The AP3603 enters external synchronous operation mode when edge of FSYN turns off the external MOSFET connected to DRV2. If the high level input of FSYN continues more than 1 cycle of internal CLK, the AP3603 change the synchronization from external clock to internal oscillator. The input signal to the FSYN pin for synchronization must be 50% duty. FSYN pin must be open in case of no use of external synchronous operation. The AP3603 does not operate if FSYN pin connect to GND because internal OSC does not generate the clock signal. At the case of using an external synchronous operation, FSYN pin must be open before and during startup. And input the external clock to FSYN pin after V8 voltage reach the target (8V ) approximately. Hi入力時は内部CLK優先 固定オフ時間 外部同期可能 外部同期可能 外部同期開始 外部同期解除 内部発振 50% 内部CLK 内部発振 50% 50% 50% 外部同期 FSYN(外部CLK) DRV1 DRV2 Figure 2. External Synchronous Timing Chart Internal OSC Internal OSC External SYNC Precede internal clock in input High Fixed OFF time Available external Sync Available external Sync Enter external Sync Exit external Sync FSYN (External CLK) Internal CLK DRV1 DRV2 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |