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Z89167 Datasheet(PDF) 14 Page - Zilog, Inc.

Part # Z89167
Description  DTAD CONTROLLERS
PDF  22 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z89167 Datasheet(HTML) 14 Page - Zilog, Inc.

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Z89165/166/167/168/169
DTAD CONTROLLERS
CP96TAD0103
ZILOG
AC CHARACTERISTICS
Z89165/166
External I/O or Memory Read and Write Timing Table
V
CC
T
A=0°C to +70°C
No
Symbol
Parameter
Note [4]
Min
Max
Units
Notes
1
TdA(AS)
Address Valid to /AS Rise Delay
5.0V
25
ns
[2,3]
2
TdAS(A)
/AS Rise to Address Float Delay
5.0V
35
ns
[2,3]
3
TdAS(DR)
/AS Rise to Read Data Req’d Valid
5.0V
150
ns
[1,2,3]
4
TwAS
/AS Low Width
5.0V
35
ns
[2,3]
5
TdAZ(DS)
Address Float to /DS Fall
5.0V
-3
ns
6
TwDSR
/DS (Read) Low Width
5.0V
125
ns
[1,2,3]
7
TwDSW
/DS (Write) Low Width
5.0V
75
ns
[1,2,3]
8
TdDSR(DR)
/DS Fall to Read Data Req’d Valid
5.0V
90
ns
[1,2,3]
9
ThDR(DS)
Read Data to /DS Rise Hold Time
5.0V
0
ns
[2,3]
10
TdDS(A)
/DS Rise to Address Active Delay
5.0V
40
ns
[2,3]
11
TdDS(AS)
/DS Rise to /AS Fall Delay
5.0V
35
ns
[2,3]
12
TdR/W(AS)
R//W Valid to /AS Rise Delay
5.0V
25
ns
[2,3]
13
TdDS(R/W)
/DS Rise to R//W Not Valid
5.0V
35
ns
[2,3]
14
TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay
5.0V
40
ns
[2,3]
15
TdDS(DW)
/DS Rise to Write Data Not Valid Delay
5.0V
25
ns
[2,3]
16
TdA(DR)
Address Valid to Read Data Req’d Valid
5.0V
180
ns
[1,2,3]
17
TdAS(DS)
/AS Rise to /DS Fall Delay
5.0V
48
ns
[2,3]
18
TdDI(DS)
Data Input Setup to /DS Rise
5.0V
50
ns
[1,2,3]
19
TdDM(AS)
/DM Valid to /AS Fall Delay
5.0V
20
ns
[2,3]
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
[4] 5.0 V
± 0.5 V.
Standard Test Load
All timing references use 0.9 V
CC for a logic 1 and 0.1 VCC for a logic 0.



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