AP22850

Document number: DS36540 Rev. 2 - 2

9 of 14

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March 2015

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AP22850

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Application Information

Theory of Operation

The AP22850 is a load switch that can be used to isolate or power-down part of a system in order to reduce power consumption, particularly in

battery-powered devices. The PMOS pass element in AP22850 is turned on when the EN pin is pulled high. This provides a controlled current

source to decrease the voltage on the SS pin to GND, effectively turning on the PMOS pass switch and connecting VOUT to VIN.

During the turn-on phase, once the SS voltage reaches close to GND, the PMOS pass switch is fully enhanced with maximum available

overdrive. Power is deemed to be good and the Power Good (PG) output is pulled high via an external pull-up resistor. The rise-time on VOUT is

controlled by the value of the external capacitor between the SS and VOUT pin.

When EN is pulled low, the switch turns off and isolates VOUT from VIN. In addition, PG is pulled to indicate that the power is no longer good.

The discharge pin keeps VOUT grounded while EN is low. The fall time on VOUT is largely controlled by the value of the discharge resistor and

the capacitance on the output.

Input and Output Voltage

The Input Voltage (VIN) should be between 4.5V and 11V. With the switch is activated, the Output Voltage (VOUT) will be the input voltage

minus the voltage drop across the device.

Enable

The GPIO compatible EN input allows the output current to be switched on and off. A high signal (switch on) should be at least 1V, and the low

signal (switch off) no higher than 0.5V.

This pin should not be left floating. It is advisable to hold EN low when applying or removing power.

VBIAS

The VBIAS input provides a positive power supply to the controller circuitry. It should be set in the range of 2.5V to 5.5V. VBIAS signal is

essential for the device to power up and should be set before the switch is enabled.

Power Good

Power Good is an open-drain output that indicates when the pass switch is enhanced enough to deliver current to the load. PG is high (open-

drain high impedance) when power is deemed good, and low when the power is deemed to not be good.

PG can be pulled up to any voltage to a maximum of 11V, although it is recommended to pull it up to VOUT with a resistor greater than 20k

Ω.

The advantage of pulling up PG to VOUT is that when EN is low, VOUT is also grounded. Thus, no power is wasted in the pull-up resistor.

If this feature is not required, then PG pin can be left floating

Input and Output Capacitors

AP22850 does not require any capacitor on VIN for successful operation. In addition, this device has no input-to-output capacitor ratio stipulation

to account for current through the body diode. However, to minimize voltage dip on VIN due to inrush current at start-up, a capacitor can be

place on VIN.

For heavier loads, it is recommended that the VIN and VOUT trace lengths be kept to a minimum.

In addition, a bulk capacitor (≥ 10μF) may also

be placed close to the VOUT pin. If using a bulk capacitor on VOUT, it is important to control the inrush current by choosing an appropriate soft-

start time in order to minimize the droop on the input supply.