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CP2114 Datasheet(PDF) 21 Page - Silicon Laboratories

Part # CP2114
Description  SINGLE-CHIP USB AUDIO TO I2S DIGITAL AUDIO BRIDGE
PDF  44 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CP2114 Datasheet(HTML) 21 Page - Silicon Laboratories

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CP2114
Rev. 1.1
21
5.6. CP2114 Clock Configuration
The CP2114 always reports its capabilities to the USB host at a sample rate of 48 kHz and sample size of 16 bits.
For source audio files differing from this format the USB host will automatically perform sample rate conversion.
The CP2114 has the following configuration options:
Table 19 shows all possible clock configuration settings for the CP2114. The CP2114 divides the USB source clock
by 4 so a clock of 48 MHz provides the 12 MHz clock needed for USB. The CP2114 divides the system clock by 4
to derive MCLK. So a 48 MHz system clock will generate MCLK = 12 MHz. If the CP2114 is configured to operate
in Asynchronous mode, it will automatically use explicit feedback to the host. If it is configured for Synchronous
mode, then the sample synchronization method is noted in the table. There are a number of invalid clocking
configurations that result from either the USB clock not resulting in 12 MHz or the MCLK/LRCK not being an
integer divisor. Operating in asynchronous mode is recommended because it best accommodates any mismatch in
host/CP2114 clocks. Operating in synchronous mode requires the CP2114 to adjust its internal oscillator to match
the host sample rate, or to periodically drop or repeat an audio sample if SYSCLK is driven by an External Clock.
Table 18. Clock Configuration Options
Configuration Parameter
Options
Stream Type
Asynchronous
Synchronous
USB Clock Source
Internal
External
System Clock Source
Internal
External
System Clock Frequency
48 MHz
49.152 MHz
MCLK/LRCK Ratio
250
256
Table 19. Valid Clock Configuration Modes
Mode
USB
Clock
(USBCLK)
Source
System
Clock
(SYSCLK)
Source
Int Freq
(MHz)
MCLK/
LRCK
Ratio
Ext Osc
Freq
(MHz)
Notes
1Int
Int
48
250
NA
Lowest cost - no external clock required
Audio device must support 12.0 MHz MCLK
Sync mode: IntOsc adjusted to
accommodate clock mismatch
2
Int
Ext
48
256
49.152
Async mode: best audio quality
Sync mode: must drop/repeat samples to
accommodate clock mismatch
3Ext
Int
48
49.152
250
256
48
IntOsc frequency dictated by audio device
MCLK/LRCK ratio
Sync mode: IntOsc adjusted to
accommodate clock mismatch
4Ext
Ext
48
250
48
Audio device must support 12.0 MHz MCLK
Async mode: best audio quality
Sync mode: must drop/repeat samples to
accommodate clock mismatch



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