CAP1106 datasheet(10/48 Pages) MICROCHIP

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CAP1106

DS00001624B-page 10

 2015 Microchip Technology Inc.

4.0

COMMUNICATIONS

4.1

Communications

The CAP1106 communicates using the SMBus or I2C protocol. If the proprietary BC-Link protocol is required for your

application, please contact your Microchip representative for ordering instructions. Regardless of the communications

mechanism, the device functionality remains unchanged.

4.1.1

SMBUS (I2C) COMMUNICATIONS

The supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block.

In addition, the device supports I2C formatting for block read and block write protocols.

See Section 4.2 and Section 4.3 for more information on the SMBus bus and protocols respectively.

APPLICATION NOTE:

Upon power up, the CAP1106 will not respond to any communications for up to 15ms. After

this time, full functionality is available.

4.2

System Management Bus

The CAP1106 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial

communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in

Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1106 will not stretch the clock signal.

4.2.1

SMBUS START BIT

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the

SMBus Clock line is in a logic ‘1’ state.

4.2.2

SMBUS ADDRESS AND RD / WR BIT

The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit

is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus

Host is reading data from the slave device.

The CAP1106 responds to SMBus address 0101_000(r/w).

4.2.3

SMBUS DATA BYTES

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.2.4

SMBUS ACK AND NACK BITS

The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus

Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto-

cols.

FIGURE 4-1:

SMBus Timing Diagram

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

S - Start Condition

P - Stop Condition

THD:DAT

TSU:DAT

TSU:STA

THD:STA

TSU:STO

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