MEC1322 datasheet(345/456 Pages) MICROCHIP

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DS00001719D-page 345

MEC1322

device always provides the clock for transmit and receive operations. The serial packet is made up of eleven bits, listed

in the order they appear on the data line: start bit, eight data bits (least significant bit first), odd parity, and stop bit. Each

bit cell is from 60

μS to 100μS long.

All PS/2 Serial Channel signals (PS2CLK and PS2DAT) are driven by open drain drivers which can be pulled to VCC1

or the main power rail (+3.3V nominal) through 10K-ohm resistors.

The PS/2 controller supports a PS/2 Wake Interface that can wake the EC from the IDLE or SLEEP states. The Wake

Interface can generate wake interrupts without a clock. The PS/2 Wake Interface is only active when the peripheral

device and external pull-up resisters are powered by the VCC1 supply.

There are no special precautions to be taken to prevent back drive of a PS/2 peripheral powered by the main power well

when the power well is off, as long as the external 10K pull-up resistor is tied to the same power source as the peripheral.

29.11 Block Diagram

29.12 PS/2 Port Physical Layer Byte Transmission Protocol

The PS/2 physical layer transfers a byte of data via an eleven bit serial stream as shown in Table 29-6. A logic 1 is sent

at an active high level. Data sent from a Keyboard or mouse device to the host is read on the falling edge of the clock

signal. The Keyboard or mouse device always generates the clock signal. The Host may inhibit communication by pull-

ing the Clock line low. The Clock line must be continuously high for at least 50 microseconds before the Keyboard or

mouse device can begin to transmit its data. See Table 29-7, "PS/2 Port Physical Layer Bus States".

FIGURE 29-2:

PORT PS/2 BLOCK DIAGRAM

TABLE 29-6:

PS/2 PORT PHYSICAL LAYER BYTE TRANSMISSION PROTOCOL

Bit

Function

Start bit (always 0)

Data bit 0 (least significant bit)

Data bit 1

Data bit 2

Data bit 3

Data bit 4

Data bit 5

Data bit 6

Data bit 7 (most significant bit)

Parity bit (odd parity)

Stop Bit (always 1)

Control

Registers

PS2DAT

PS2CLK

PS/2

Channel

State

Machine

EC I/F

PS2_x

interrupt

48MHz

2 MHz

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