C868 datasheet(63/82 Pages) INFINEON

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C868

Data Sheet

V 1.0, 2003-05

Fail Save Mechanisms

The C868 offers enhanced fail save mechanisms, which allow an automatic recovery

from software upset or hardware failure :

a programmable watchdog timer (WDT), with variable time-out period from 12.8

µs to

819.2

µs at f

SYS = 40 MHz.

Programmable Watchdog Timer

To protect the system against software failure, the user’s program has to clear this

watchdog within a previously programmed time period. lf the software fails to do this

periodical refresh of the watchdog timer, an internal reset will be initiated. The software

can be designed so that the watchdog times out if the program does not work properly.

lt also times out if a software error is based on hardware-related problems.

The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate

of f

SYS/2 upto fSYS/128. The machine clock of the C868 is divided by a prescaler, a divide-

by-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be

preset to a user-programmable value via a watchdog service access in order to vary the

watchdog expire time. The lower 8 bits are reset on each service access. Figure 29

shows the block diagram of the watchdog timer unit.

Figure 29

Block Diagram of the Programmable Watchdog Timer

After a reset, the Watchdog Timer is automatically enabled. If it is disabled, it cannot be

enabled again during active mode of the device.

If the software fails to clear the

watchdog timer an internal reset will be initiated. The reset cause (external reset or reset

caused by the watchdog) can be examined by software (status flag WDTR in SCUWDT

is set). A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS (in

WDT High Byte

WDTRST

WDTREL

DISWDT

WDTIN

MUX

1:2

WDT Low Byte

WDT

Control

Clear

1:128

SYS

C868 Datasheet(PDF) 63 Page - Infineon Technologies AG

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