C868 datasheet(22/82 Pages) INFINEON

22 / 82 page

C868

Data Sheet

V 1.0, 2003-05

The PLL output frequency is determined by:

[1]

The range for the VCO frequency is given by:

100 MHz

≤ f

VCO ≤ 160 MHz

[2]

The relationship between the input frequency and VCO frequency is given by:

[3]

This gives the range for the input frequency which is given by:

6.67 MHz

≤ f

OSC ≤ 10.67 MHz

[4]

Table 5

Output Frequencies

fPLL Derived from Various Output Factors

K-Factor

fPLL

Duty

Cycle [%]

Jitter

Selected

Factor

KDIV

fVCO =

100 MHz

fVCO =

160 MHz

000B

linear depending on fVCO

at fVCO =100MHz: +/-300ps

at fVCO =160MHz: +/-250ps

additional jitter for odd Kdiv

factors tbd.

010B

51)

These odd factors should not be used (not tested because off the unsymmetrical duty cycle).

Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.

011B

100B

16.67

26.67

101B

12.5

91)

110B

11.11

17.78

111B

001B

6.25

fPLL = fVCO / K =

× f

OSC

fVCO =15 × fOSC

C868 Datasheet(PDF) 22 Page - Infineon Technologies AG

C868 Datasheet(HTML) 22 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL