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LSF0102 Datasheet(PDF) 1 Page - Texas Instruments |
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LSF0102 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 39 page ![]() LSF0101 GND Vref_A A1 EN Vref_B B1 DRY Package 6-Pin SON (Top View) 1 2 3 4 5 6 A8 B8 EN GND 10 11 20 1 LSF0108 LSF0102 GND EN Vref_A A1 A2 Vref_B B1 B2 DQE Package 8-Pin X2SON (Top View) Vref_A A2 B2 A1 B1 Vref_B GND EN YZT Package 8-Pin DSBGA (Bottom View) 1 2 3 4 5 6 7 8 D1 C1 B1 A1 D2 C2 B2 A2 4 3 2 1 5 7 6 8 RKS Package 20-Pin VQFN (Top View) Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LSF0101, LSF0102, LSF0108 SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016 LSF010x 1/2/8 Channel Bidirectional Multi-Voltage Level Translator for Open-Drain and Push-Pull Application 1 1 Features 1 • Provides Bidirectional Voltage Translation With No Direction Pin • Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Translation at 50 pF Cap Load • Supports Hot Insertion • Allow Bidirectional Voltage Level Translation Between – 0.95 V ↔ 1.8/2.5/3.3/5 V – 1.2 V ↔ 1.8/2.5/3.3/5 V – 1.8 V ↔ 2.5/3.3/5 V – 2.5 V ↔ 3.3/5 V – 3.3 V ↔ 5 V • Low Standby Current • 5 V Tolerance I/O Port to Support TTL • Low Ron Provides Less Signal Distortion • High-Impedance I/O pins For EN = Low • Flow-Through Pinout for Ease PCB Trace Routing • Latch-Up Performance Exceeds 100 mA Per JESD 17 • –40°C to 125°C Operating Temperature Range • ESD Performance Tested Per JESD 22 – 2000 V Human-Body Model (A114-B, Class II) – 200 V Machine Model (A115-A) – 1000 V Charged-Device Model (C101) 2 Applications • GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and Other Interfaces in Telecom Infrastructure • Industrial • Automotive • Personal Computing 3 Description LSF family supports up to 100 MHz up translation and greater than 100 MHz down translation at ≤ 30pF cap load and up to 40 MHz up/down translation at 50 pF cap load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO). The LSF family has bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, or SMbus). LSF family supports 5 V tolerance on IO port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels on each channel which makes it very flexible. Device Information(1) PART NUMBER PACKAGE(PINS) BODY SIZE (NOM) LSF0101 SON (6) 1.45 mm × 1.00 mm LSF0102 X2SON (8) 1.40 mm × 1.00 mm DSBGA (8) 1.90 mm × 1.00 mm SM8 (8) 2.80 mm × 2.95 mm VSSOP (8) 2.30 mm × 2.00 mm LSF0108 VQFN (20) 4.50 mm × 2.50 mm TSSOP (20) 4.40 mm × 6.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. |
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Similar Description - LSF0102 |
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