RF430CL330HCPWR datasheet(33/47 Pages) TI1

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RF430CL330H

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SLAS916C – NOVEMBER 2012 – REVISED NOVEMBER 2014

5.9

NDEF Memory

This device implements 3KB of SRAM memory that must be written with the NDEF Application data.

Table 5-31 shows the mandatory structure. The data can be accessed through the RF interface only after

the NDEF memory is correctly initialized through the serial interface (I2C or SPI).

While writing into the NDEF memory, the RF interface must be disabled by clearing the Enable RF bit in

the General Control register. After the NDEF memory is properly initialized, the RF interface can be

enabled be setting the Enable RF bit in the General Control register to 1. When the RF interface is

enabled, the basic NDEF structure is checked for correctness. If an error in the structure is detected, the

NDEF Error IRQ is triggered, and the RF interface remains disabled (the Enable RF bit in the General

Control register is cleared to 0).

If the NDEF application data must be modified through the serial interface after the RF interface is

enabled, it is recommended to read the RF Busy bit in the Status register. If the RF interface is busy,

defer disabling the RF interface until the RF transaction is completed (indicated by RF Busy bit = 0).

Figure 5-11 shows the recommended flow how to control the access to the NDEF memory.

The address range for the NDEF memory is 0x0000 to 0x0BFF.

Table 5-31. NDEF Application Data (Mandatory)

2B - CCLen

1B - Mapping version

2B - MLe = 000F9h

2B - MLc = 000F6h

Capability Container

1B - Tag = 04h

Selectable by File ID

1B - Len = 06h

NDEF Application

= E103h

The NDEF file

2B - File Identifier

NDEF File Ctrl TLV

control TLV is

Selectable

Name

2B - Max file size

mandatory

D2_7600_0085_0101h

6B - Val

1B - Read access

1B - Write access

2B - Len

NDEF File

Mandatory NDEF

xB - Binary NDEF file content

file

Selectable by File ID

yB - Unused if Len < Max file size in File Ctrl TLV

= xxyyh

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