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RF430CL330HCPWR Datasheet(PDF) 9 Page - Texas Instruments |
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RF430CL330HCPWR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 47 page ![]() SDA SCL 1/fSCL tHD,DAT tSU,DAT tHD,STA tSU,STA tHD,STA tSU,STO tSP RF430CL330H www.ti.com SLAS916C – NOVEMBER 2012 – REVISED NOVEMBER 2014 4.9 Serial Communication Protocol Timings over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP MAX UNIT tSPIvsI2C Time after power-up or reset until SCMS/CS is sampled for SPI or I2C decision(1) 1 10 ms tReady Time after power-up or reset until device is ready to communicate using SPI or I2C(2) 20 ms (1) The SCMS/CS pin is sampled after tSPIvsI2C(MIN) at the earliest and after tSPIvsI2C(MAX) at the latest. (2) The device is ready to communicate after tReady(MAX) at the latest. 4.10 I 2C Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1) TEST PARAMETER VCC MIN TYP MAX UNIT CONDITIONS SCL clock frequency (with Master supporting clock stretching according to I2C standard, or when the device is 3.3 V 0 400 kHz not being addressed) fSCL write 3.3 V 0 120 kHz SCL clock frequency (device being addressed by Master not supporting clock stretching) read 3.3 V 0 100 kHz fSCL ≤ 100 kHz 4 tHD,STA Hold time (repeated) START 3.3 V µs fSCL > 100 kHz 0.6 fSCL ≤ 100 kHz 4.7 tSU,STA Setup time for a repeated START 3.3 V µs fSCL > 100 kHz 0.6 tHD,DAT Data hold time 3.3 V 0 ns tSU,DAT Data setup time 3.3 V 250 ns tSU,STO Setup time for STOP 3.3 V 4 µs tSP Pulse duration of spikes suppressed by input filter 3.3 V 6.25 75 ns Figure 4-1. I2C Mode Timing Copyright © 2012–2014, Texas Instruments Incorporated Specifications 9 Submit Documentation Feedback Product Folder Links: RF430CL330H |
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