GS1661 datasheet(30/84 Pages) SEMTECH

30 / 84 page

GS1661 HD/SD SDI Receiver

Data Sheet

53751 - 3

September 2012

30 of 84

4.6.2 Signal Interruption

The device tolerates a signal interruption of up to 10

μs without unlocking, as long as no

TRS words are deleted by this interruption. If a signal interruption of greater than 10

μs

is detected, the lock detection algorithm may lose the current data rate, and LOCKED

will de-assert until the data rate is re-acquired by the lock detection block.

4.7 SMPTE Functionality

4.7.1 Descrambling and Word Alignment

The GS1661 performs NRZI to NRZ decoding and data descrambling according to

SMPTE 292/SMPTE 259M-C and word-aligns the data to TRS sync words.

When operating in manual mode (AUTO/MAN = LOW), the device only carries out

SMPTE decoding, descrambling and word alignment when the SMPTE_BYPASS pin is set

HIGH and the DVB_ASI pin is set LOW.

When operating in Auto mode (AUTO/MAN = HIGH), the GS1661 carries out

descrambling and word alignment to enable the detection of TRS sync words. When two

consecutive valid TRS words (SAV and EAV), with the same bit alignment have been

detected, the device word-aligns the data to the TRS ID words.

TRS ID word detection is a continuous process. The device remains in SMPTE mode until

TRS ID words fail to be detected.

NOTE: Both 8-bit and 10-bit TRS headers are identified by the device.

4.8 Parallel Data Outputs

The parallel data outputs are aligned to the rising edge of the PCLK.

4.8.1 Parallel Data Bus Buffers

The parallel data bus, status signal outputs and control signal input pins are all

connected to high-impedance buffers.

The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and

IO_GND pins.

All output buffers (including the PCLK output), are set to high-impedance in Reset mode

(RESET_TRST = LOW).

GS1661 Datasheet(PDF) 30 Page - Semtech Corporation