GS1670 datasheet(10/126 Pages) SEMTECH

10 / 126 page

GS1670 HD/SD SDI Receiver

Data Sheet

53831 - 2

September 2012

10 of 126

A9, A10, B8,

B9, B10,C8,

C9, C10, E9,

E10

DOUT18, 17, 19,

16, 15, 12, 14, 13,

10, 11

Output

PARALLEL DATA BUS

Please refer to the Output Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

20-bit mode

20bit/10bit = HIGH

SMPTE mode (SMPTE_BYPASS = HIGH

and DVB_ASI = LOW):

Luma data output for SD and HD data

rates.

DVB-ASI mode (SMPTE_BYPASS = LOW

and DVB_ASI = HIGH):

Not defined

Data-Through mode (SMPTE_BYPASS =

LOW and DVB_ASI = LOW):

Data output

10-bit mode

20bit/10bit = LOW

SMPTE mode (SMPTE_BYPASS = HIGH

and DVB_ASI = LOW):

Multiplexed Luma/Chroma data output

for SD and HD data rates.

DVB-ASI mode (SMPTE_BYPASS = LOW

and DVB_ASI = HIGH):

8b/10b decoded DVB-ASI data

Data-Through mode (SMPTE_BYPASS =

LOW and DVB_ASI = LOW):

Data output

A_VDD

Input Power

POWER pin for analog circuitry. Connect to 3.3V DC analog.

B2, C3, C4

PLL_VDD

Input Power

POWER pins for the Reclocker PLL. Connect to 1.2V DC analog.

B3, F2, G1,

G2, G4

RSV

These pins must be left unconnected.

VCO_GND

Input Power

GND pin for the VCO. Connect to analog GND.

B7, D9, G9,

IO_GND

Input Power

GND connection for digital I/O. Connect to digital GND.

C1, D1

SDI, SDI

Analog Input

Serial Digital Differential Input.

C2, D2, D3,

E3, F3

A_GND

Input Power

GND pins for sensitive analog circuitry. Connect to analog GND.

C7RESET_TRST

Input

CONTROL SIGNAL INPUT

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to reset the internal operating conditions to default settings

and to reset the JTAG sequence.

Normal mode (JTAG/HOST = LOW):

When LOW, all functional blocks are set to default conditions and

all digital output signals become high impedance.

When HIGH, normal operation of the device resumes.

JTAG test mode (JTAG/HOST = HIGH):

When LOW, all functional blocks are set to default and the JTAG test

sequence is reset.

When HIGH, normal operation of the JTAG test sequence resumes

after RESET_TRST is de-asserted.

Table 1-1:Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

GS1670 Datasheet(PDF) 10 Page - Semtech Corporation

GS1670 Datasheet(HTML) 10 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL