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PE42020 Datasheet(PDF) 21 Page - Peregrine Semiconductor |
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PE42020 Datasheet(HTML) 21 Page - Peregrine Semiconductor |
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21 / 25 page ![]() PE42020 UltraCMOS® True DC RF Switch DOC-23814-3 – (12/2014) Page 21 www.psemi.com Evaluation Kit The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine's PE42020. The RF common port is connected through a 50 Ω transmission line via the SMA connector, J3. RF1 and RF2 ports are connected through 50 Ω transmission lines via SMA connectors J1 and J2 respectively. A 50Ω through trans- mission line is available via SMA connectors J5 and J6, which can be used to de-embed the loss of the PCB. J4 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 62 mils. The top RF layer is Rogers 4350B material with a thickness of 6.6 mils and the Ɛ r = 3.66. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 13 mils, trace gaps of 10.5 mils and metal thickness of 3.4 mils. For the true performance of the PE42020 to be realized, the PCB must be designed in such a way that RF trans- mission lines and sensitive DC I/O traces are well isolated from one another. Figure 29 • Evaluation Kit Layout for PE42020 |
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