AD8284 datasheet(16/28 Pages) AD

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AD8284

Data Sheet

Rev. D | Page 16 of 28

CLOCK DUTY CYCLE CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD8284 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD8284.

When the DCS is on, noise and distortion performance are

nearly flat for a wide range of duty cycles. However, some appli-

cations may require the DCS function to be off. If so, note that

the dynamic range performance can be affected when operating in

this mode. See Table 10 for more details on using this feature.

The duty cycle stabilizer uses a delay locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

CLOCK JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter.

In cases where aperture jitter may affect the dynamic range of the

AD8284, treat the clock input as an analog signal. Separate

power supplies for clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

Low jitter, crystal controlled oscillators make the best clock

sources, such as the Valpey Fisher VFAC3 series. If the clock is

generated from another type of source by using the sequential

steps of gating, dividing, or other methods, it should be retimed

by the original clock during the last step in that sequence.

See the AN-501 Application Note and the AN-756 Application

Note for more information about how jitter performance relates

to ADCs.

SDI AND SDO PINS

The SDI and SDO pins are required to operate the SPI. The SDI pin

has an internal 30 kΩ pull-down resistor that pulls this pin low and

is 1.8 V and 3.3 V tolerant. The SDO output pin is 3.3 V logic.

SCLK PIN

The SCLK pin is required to operate the SPI. It has an internal

30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V

and 3.3 V tolerant.

CS PIN

The CS pin is required to operate the SPI. It has an internal 70 kΩ

pull-up resistor that pulls this pin high and is both 1.8 V and

3.3 V tolerant.

RBIAS PIN

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a

resistor other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, it is imperative

that at least a 1.0% tolerance on this resistor be used to achieve

consistent performance.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD8284. This is gained up internally by a factor of 2, setting

VREF to 1.0 V, which results in a full-scale differential input span

of 2.0 V p-p for the ADC. VREF is set internally by default, but

the VREF pin can be driven externally with a 1.0 V reference to

achieve more accuracy. However, the AD8284 is not specified

for ADC full-scale ranges below 2.0 V p-p.

When applying decoupling capacitors to the VREF pin, use

ceramic, low ESR capacitors. Place these capacitors close to the

reference pin and on the same layer of the PCB as the AD8284.

The VREF pin should have both a 0.1 μF capacitor and a 1 μF

capacitor connected in parallel to the analog ground. These

capacitor values are recommended for the ADC to properly

settle and acquire the next valid sample.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD8284, it is recommended

that two separate 1.8 V supplies and two separate 3.3 V supplies

be used: one supply each for analog 1.8 V (AVDD18x), digital

1.8 V (DVDD18x), analog 3.3 V (AVDD33x), and digital 3.3 V

(DVDD33x). If only one supply is available for both analog and

digital, for example, AVDD18x and DVDD18x, route the supply

to AVDD18x first and then tap the supply off and isolate it with

a ferrite bead or a filter choke preceded by decoupling

capacitors for the DVDD18x. The same method is used for the

analog and digital 3.3 V supplies. Use several decoupling

capacitors on all supplies to cover both high and low

frequencies. Locate these capacitors close to the point of entry

at the printed circuit board (PCB) level and close to the AD8284

using minimal trace lengths.

The 12 power supply pins are separated into four power supply

domains, AVDD18, AVDD33, DVDD18, and DVDD33. Each

pin within a domain must be powered simultaneously, but each

domain can be turned on independently of the other domains.

A single PCB ground plane should be sufficient when using the

AD8284. With proper decoupling and smart partitioning of the

analog, digital, and clock sections of the PCB, optimum perfor-

mance can be easily achieved.

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