ADC0851 datasheet(18/36 Pages) NSC

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20 Memory Access Modes

The ADC08518 has an internal RAM with sixteen memory

locations (one location for the upper limit and one for the

lower limit for each of the 8 input channels) Each memory

location is 8 bits wide An 8-bit limit word representing an

upper or lower limit boundary can either be written to or read

from the RAM The ADC0851 uses only four memory loca-

tions for the four boundary limits corresponding to the two

inputs The eight channel ADC0858 however makes use of

all sixteen memory locations

Each memory location is accessed by a specific address as

shown by Table II(a) and (b) Note that even addresses cor-

respond to the lower limits while the odd addresses corre-

spond to the upper limits The ADC0851 and ADC0858 both

use 4 bits (A3

A0) to address the RAM however

ADC0851 decodes only the two LSBs of the address data

while ignoring the two MSBs

TABLE IIa RAM Address and

Limit Data for ADC0851

RAM Address

Corresponding

Channel and Limit

CH0 – Lower Limit

CH0 – Upper Limit

CH1 – Lower Limit

CH1 – Upper Limit

Limit Data (ADC0851)

TABLE IIb RAM Address and

Limit Data for ADC0858

RAM Address

Corresponding

Channel and Limit

CH0 – Lower Limit

CH0 – Upper Limit

CH1 – Lower Limit

CH1 – Upper Limit

CH2 – Lower Limit

CH2 – Upper Limit

CH3 – Lower Limit

CH3 – Upper Limit

CH4 – Lower Limit

CH4 – Upper Limit

CH5 – Lower Limit

CH5 – Upper Limit

CH6 – Lower Limit

CH6 – Upper Limit

CH7 – Lower Limit

CH7 – Upper Limit

Limit Data (ADC0858)

21 WRITE ONE LIMIT

This mode is used to update a single memory location in the

limit RAM An 8-bit limit word is written to the location point-

ed to by the limit address From Table I we can see that to

initiate the operation of the device in the ‘‘write one limit’’

mode the mode address has to be1001 The data format

for the input word is as shown below

Data Input (DI) WordADC0851 or ADC0858

TLH11021 – 31

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