ADC0851 datasheet(23/36 Pages) NSC

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30 Watchdog Mode (Continued)

The device will read the new input word and configure to a

different mode if CS is high for less than eight oscillator

clock periods for the ADC0851 and less than thirty-two os-

cillator clock periods for the ADC0858

Once a boundary limit is crossed INT goes low Moreover

for ADC0851 COMPL goes low if a lower limit is crossed

whereas COMPH goes low if an upper limit is crossed If the

input signals exceed both the upper and lower boundary

limits then both COMPL and COMPH would go low

To output data after a limit crossing occurs (ie after INT

goes low) CS should be brought low Note that INT

COMPL and COMPH would remain low as long as CS

doesn’t go low

After CS goes low INT

COMPL and

COMPH go high and one clock cycle later output data is

transmitted starting at the first rising edge of CLK however

the data is valid at the falling edge of CLK (

Figure 7 )

32 LIMIT CROSSING DETECTION

When the ADC08518 is configured in the watchdog mode

the device operates as a window comparator First the low-

er window limit (stored in the RAM) for CH0 is compared

against the input voltage at CH0 If the input voltage is

greater than the lower limit then no interrupt is generated

Next the upper window limit for CH0 is compared against

CH0 input voltage If the input voltage is less than the upper

window limit then no interrupt is generated for CH0 and the

device starts a similar comparison cycle for the next chan-

nel (CH1) Note that the lower limit can be greater than the

upper limit in this case the device will flag the microproces-

sor if the input signal falls inside a window

TABLE IVa Channel Tag Address

and Status (ADC0851)

Tag

Tag Address

Corresponding Limit

and Channel

0000

Lower LimitCH0

0001

Upper LimitCH0

0010

Lower LimitCH1

0011

Upper LimitCH1

TLH11021 – 43

TABLE IVb Channel Tag Address

and Status (ADC0858)

Tag

Tag Address

Corresponding Limit

and Channel

0000

Lower LimitCH0

0001

Upper LimitCH0

0010

Lower LimitCH1

0011

Upper LimitCH1

0100

Lower LimitCH2

0101

Upper LimitCH2

0110

Lower LimitCH3

0111

Upper LimitCH3

1000

Lower LimitCH4

1001

Upper LimitCH4

1010

Lower LimitCH5

1011

Upper LimitCH5

1100

Lower LimitCH6

1101

Upper LimitCH6

1110

Lower LimitCH7

1111

Upper LimitCH7

TLH11021 – 44

Each comparison takes 2 ms thus a total of 4 ms is required

per channel

When in watchdog mode the device will continuously cycle

through the input channels until an input that has crossed its

preset window limit is detected When this occurs a logical

‘‘1’’ is stored in the MSB (bit S3 for ADC0851 and S15 for

ADC0858) position of the status register In addition the tag

IV(a) and (b) for ADC0851 and ADC0858 respectively) Note

that the tag address indicates which channel crossed which

limit Once the tag register is updated after the first limit is

crossed the device will once more cycle through the re-

maining channels and compare the input voltages against

ADC0851 Datasheet(PDF) 23 Page - National Semiconductor (TI)

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