ADC10321 datasheet(3/16 Pages) NSC

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Pin Descriptions and Equivalent Circuits

No.

Symbol

Equivalent Circuit

Description

Analog I/O

Analog Input signal to be converted. Conversion

range is V

REF+ StoVREF− S.

REF+ F

Analog input that goes to the high side of the

reference ladder of the ADC. This voltage should

force V

REF+ S to be in the range of 2.3V to 4.0V.

REF+ S

Analog output used to sense the voltage at the top

of the ADC reference ladder.

REF− F

Analog input that goes to the low side of the

reference ladder of the ADC. This voltage should

force V

REF− S to be in the range of 1.3V to 3.0V.

REF− S

Analog output used to sense the voltage at the

bottom of the ADC reference ladder.

CLK

Converter digital clock input. V

IN is sampled on the

falling edge of CLK input.

8PD

Power Down input. When this pin is high, the

converter is in the Power Down mode and the data

output pins are in a high impedance state.

Output Enable pin. When this pin and the PD pin

are low, the output data pins are active. When this

pin or the PD pin is high, the output data pins are in

a high impedance state.

thru

and

thru

D0 -D9

Digital Output pins providing the 10 bit conversion

results. D0 is the LSB, D9 is the MSB. Valid data is

present just after the falling edge of the CLK input.

3, 7,

Positive analog supply pins. These pins should be

connected to a clean, quiet voltage source of +5V.

A and VD should have a common supply and be

separately bypassed with 10µF to 50µF capacitors

in parallel with 0.1µF capacitors.

5, 10

Positive digital supply pins. These pins should be

connected to a clean, quiet voltage source of +5V.

A and VD should have a common supply and be

separately bypassed with 10µF to 50µF capacitors

in parallel with 0.1µF capacitors.

ADC10321 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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