ADC10321 datasheet(12/16 Pages) NSC

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Applications Information (Continued)

The V

REF+ F and VREF− F pins should each be bypassed to

AGND with 10µF tantalum or electrolytic and 0.1µF ceramic

capacitors. The circuit of

Figure 6 may be used if it is desired

to obtain precise reference voltages. The LMC6082 in this

circuit was chosen for its low offset voltage, low voltage

rail-to-rail capability and low cost.

Since the current flowing through the sense lines (those lines

associated with V

REF+ S and VREF− S) is essentially zero,

there is negligible voltage drop across any resistance in se-

ries with these sense pins and the voltage at the inverting in-

put of the op-amp accurately represents the voltage at the

top (or bottom) of the ladder. The op-amp drives the force in-

put, forcing the voltage at the ends of the ladder to equal the

voltage at the op-amp’s non-inverting input, plus any offset

voltage. For this reason, op-amps with low V

OS, such as the

LMC6081 and LMC6082, should be used for this application.

Voltages at the reference sense pins (V

REF+ S and VREF−S)

should be within the range specified in the Operating Ratings

table (2.3V to 4.0V for V

REF+ and 1.3V to 3.0V for VREF−).

Any device used to drive the reference pins should be able to

source sufficient current into the V

REF+ F pin and sink suffi-

cient current from the V

REF− F pin when the ladder is at its

minimum value of 850 Ohms.

The reference voltage at the top of the ladder (V

REF+) may

take on values as low as 1.0V above the voltage at the bot-

tom of the ladder (V

REF−) and as high as (VA - 1.0V) Volts.

The voltage at the bottom of the ladder (V

REF−) may take on

values as low as 1.3 Volts and as high as 3.0V. However, to

minimize noise effects and ensure accurate conversions, the

total reference voltage range (V

REF+-VREF−) should be a

minimum of 2.0V and a maximum of 2.7V.

DS100897-19

FIGURE 5. Better low component count reference biasing

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