Functional Description

The ADC12191 is a monolithic CMOS analog-to-digital con-

verter capable of converting analog input signals into 12-bit

digital words at 10 megasamples per second (MSPS). This

device utilizes a proprietary pipeline architecture and algo-

rithm to minimize die size and power consumption. The

ADC12191 uses self-calibration and digital error correction

to maintain accuracy and performance over temperature.

The ADC12191 has an input sample-and-hold amplifier and

internal reference buffer. The analog input and the reference

voltage are converted to differential signals for internal use.

Using differential signals in the analog conversion core re-

duces crosstalk and noise pickup from the digital section and

power supply.

The pipeline conversion core has 15 sequential signal pro-

cessing stages. Each stage receives an analog signal from

the previous stage (called “residue”) and produces a 1-bit

digital output that is sent to the digital correction module. At

each stage the analog signal received from the previous

stage is compared to an internally generated reference level.

It is then amplified by a factor of 2, and, depending on the

output of the comparator, the internal reference signal may

be subtracted from the amplifier output. This produces the

residue that is passed to the next stage.

The calibration module is activated at power-on or by user

request. During calibration the conversion core is put into a

special mode of operation in order to determine inherent er-

rors in the analog conversion blocks and to determine cor-

rection coefficients for each digital output bit from the con-

version core and stores these coefficients in RAM. The

digital correction module uses the coefficients in RAM to

convert the raw data bits from the conversion core into the

12-bit digital output code.

Applications Information

1.0 Analog Inputs.

The ADC12191 has two single-ended analog inputs. V

the reference input and V

1.1 Reference Input The V

accurate, stable reference voltage source. of 1.8V to 2.2V,

and bypassed to a clean, quiet point in analog ground.

1.2 Analog Signal Input The V

a low impedance signal source that does not add any distor-

tion to the input signal. The ground reference for the V

put is the V

a clean, quiet point in analog ground.

2.0 Digital Inputs

The ADC12191 has four digital inputs. They are CLOCK,

CAL, OE and PD.

2.1 CLOCK The CLOCK signal drives an internal phase de-

lay loop to create timing for the ADC. The clock input should

be driven with a stable, low phase jitter TTL level clock signal

in the range of 1 to 10 MHz. The trace carrying the clock sig-

nal should be as short as possible. This trace should not

cross any other signal line, analog or digital, not even at 90˚.

A 100 Ohm resistor should be placed in series with the

CLOCK pin, as close to the pin as possible.

2.2 CAL The level sensitive CAL input must be pulsed high

for at least three clock cycles to begin ADC calibration. For

best performance, calibration should be performed about ten

sceonds after power up, after resetting the ADC, and after

the temperature has changed by more than 50˚C since the

last calibration was performed.

Calibration should be performed at the same clock fre-

quency that the ADC12191 will be used for conversions to

minimize offset errors. Calibration takes 4000 clock cycles.

Irrelevant data may appear during the calibration cycle.

DS101040-22

FIGURE 4. Reset and Calibration Timing

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