AD7761BSTZ datasheet(35/69 Pages) AD

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Data Sheet

AD7761

Rev. 0 | Page 35 of 69

SPI Interface Details

Each SPI access frame is 16 bits long. The MSB (Bit 15) of the

SDI command is the R/W bit; 1 = read and 0 = write. Bits[14:8]

of the SDI command are the address bits.

The SPI control interface uses an off frame protocol. This means

that the master (FPGA/DSP) communicates with the AD7761 in

two frames. The first frame sends a 16-bit instruction (R/W,

address, and data) and the second frame is the response where

the AD7761 sends 16 bits back to the master.

During the master write command, the SDO output contains

eight leading zeros, followed by eight bits of data, as shown in

Figure 53.

Figure 54 shows the off frame protocol. Register access responses

are always offset by one CS frame. In Figure 54, the response

(read RESP 1) to the first command (CMD 1) is output by the

AD7761 during the following CS frame at the same time as the

second command (CMD 2) is being sent.

SCLK

SDI

SDO

CMD 1

CMD 2

READ RESP 1

Figure 54. Off Frame Protocol

SPI Control Interface Error Handling

The AD7761 SPI control interface detects whether it has

received an illegal command. An illegal command is a write to a

read only register, a write to a register address that does not

exist, or a read from a register address that does not exist. If any of

these illegal commands are received by the AD7761, the device

responds with an error output of 0x0E00.

SPI Reset Configuration

After a power-on or reset, the AD7761 default configuration is set

to the following low current consumption settings:



Focus power mode with MCLK/32.



Interface configuration of DCLK = MCLK/8, header

output enabled, and CRC disabled.



Filter configuration of Channel Mode A and Channel Mode B

is set to sinc5 and decimation = ×1024. Channel mode

select is set to 0x00, and all channels are assigned to

Channel Mode A.



Channel configuration of Channel 0 to Channel 7 is enabled,

with the analog input buffers enabled. The reference precharge

buffers are disabled. The offset, gain, and phase calibration

are set to the zero position.



Continuous conversion mode is enabled.

SPI CONTROL FUNCTIONALITY

SPI control offers the superset of flexibility and diagnostics to

the user. The following sections highlight the functionality and

diagnostics offered when SPI control is used.

After any change to these configuration register settings, the

user must provide a sync signal to the AD7761 through either

the SPI_SYNC command, or by applying the appropriate pulse

to the START pin or SYNC_IN pin to ensure that the configuration

changes are applied correctly to the ADC and digital filters.

Channel Configuration

The AD7761 has eight fully differential analog input channels.

The channel configuration registers allow the channels to be

individually configured to adapt to the measurement required

on that channel. Channels can be enabled or disabled using the

channel standby register, Register 0x00. Analog input and

reference precharge buffers can be assigned per input terminal.

Gain, offset, and phase calibration can be controlled on a per

channel basis using the calibration registers. See the Per

Channel Calibration Gain, Offset, and Sync Phase section for

more information.

Channel Modes

In SPI control mode, the user can set up two channel modes,

Channel Mode A (Register 0x01), and Channel Mode B

(Register 0x02). Each channel mode register can have a specific

filter type and decimation ratio. Using the channel mode select

Channel Mode A or Channel Mode B, which maps that mode to

the required ADC channels. These modes allow different filter

types and decimation rates to be selected and mapped to any of the

ADC channels.

When different decimation rates are selected on different channels,

the AD7761 outputs a data ready signal at the fastest selected

decimation rate. Any channel that runs at a lower output data rate

is updated only at that slower rate. In between valid result data, the

data for that channel is set to zero and the repeated data bit is set in

the header status bits to distinguish it from a real conversion result

(see the ADC Conversion Output: Header and Data section for

more information).

On the AD7761, consider Channel Mode A as the primary group.

In this respect, it is recommended that there always be at least one

channel assigned to Channel Mode A. If all eight channels of the

AD7761 are assigned to Channel Mode B, conversion data is not

output on the data interface for any of the channels.

Table 21. Channel Mode A/Channel Mode B, Register 0x01

and Register 0x02

Bits

Bit Name

Setting

Description

Reset

Access

FILTER_TYPE_x

Filter output

0x1

Wideband filter

Sinc5 filter

[2:0]

DEC_RATE_x

Decimation rate

0x5

000 to

101

×32 to ×1024

AD7761BSTZ Datasheet(PDF) 35 Page - Analog Devices

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