AD7761BSTZ datasheet(16/69 Pages) AD

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AD7761

Data Sheet

Rev. 0 | Page 16 of 69

Pin No.

Mnemonic

Type1

Description

12, 13,

14, 15

MODE0/GPIO0,

MODE1/GPIO1,

MODE2/GPIO2,

MODE3/GPIO3

DI/DI/O

Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.

In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling

power consumption, DCLK frequency, and the ADC conversion type, allowing one-shot

conversion operation.

In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-

purpose input/output pins (GPIO4 to GPIO0).

ST0/CS

Standby 0/Chip Select Input.

In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.

In SPI control mode, this pin is the active low chip select input to the SPI control interface.

ST1/SCLK

Standby 1/Serial Clock Input.

In pin control mode, a Logic 1 places Channel 4 to Channel 7 into standby mode.

In SPI control mode, this pin is the serial clock input pin for the SPI control interface.

DEC1/SDI

Decimation Rate Control Input 1/Serial Data Input.

In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.

In SPI control mode, this pin is the serial data input pin used to write data to the AD7761 register

bank.

DEC0/SDO

DI/O

Decimation Rate Control Input 0/Serial Data Output.

In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.

In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7761

registers.

DOUT7

DI/O

Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDYE. This pin acts

as a digital input from a separate AD7761 device if configured in a synchronized multidevice

daisy chain when the FORMATx pins are configured as 01. To use the AD7761 in a daisy chain, hardwire

the FORMATx pins as either 01, 10, or 11, depending on the best interfacing format for the application.

When FORMATx is set to 10 or 11, connect this pin to ground through a pull-down resistor.

DOUT6

DI/O

Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDYE. This pin acts

as a digital input from a separate AD7761 device if configured in a synchronized multidevice

daisy chain. To use this pin in a daisy chain, hardwire the FORMATx pins as either 01, 10, or 11,

depending on the best interfacing format for the application.

DOUT5

Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.

DOUT4

Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.

DOUT3

Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.

DOUT2

Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.

DOUT1

Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.

DOUT0

Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY

DCLK

ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (DSP/FPGA).

This pin is synchronous with DRDYE and any conversion data output on DOUT0 to DOUT7 and is

derived from the MCLK signal. This pin is unrelated to the control SPI interface.

DRDY

Data Ready. Periodic signal output framing the conversion results from the eight ADCs. This pin

is synchronous to DCLK and DOUT0 to DOUT7.

RESETE

Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to

perform a hard or soft reset.

XTAL1

Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND.

XTAL2/MCLK

Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this

configuration.

External crystal: XTAL2 is connected to the external crystal.

LVDS: a second LVDS input is connected to this pin.

CMOS clock: this pin operates as an MCLK input. CMOS input with logic level of IOVDD/DGND.

DGND

Digital Ground. This pin is nominally 0 V.

DREGCAP

Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality,

low ESR, 10 μF capacitor. For optimum performance, use a decoupling capacitor with an ESR

specification between 50 mΩ and 400 mΩ. This pin is not for use in circuits external to the

AD7761. For 1.8 V IOVDD operation, connect this pin to IOVDD via an external trace to provide

power to the digital processing core.

AD7761BSTZ Datasheet(PDF) 16 Page - Analog Devices

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