AD9613 datasheet(27/36 Pages) AD

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Data Sheet

AD9613

Rev. C | Page 27 of 36

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 57, the power dissipated by the AD9613 is

proportional to its sample rate. The data in Figure 57 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.5

0.4

0.3

0.2

0.1

100

120

140

160

180

200

220

240

ENCODE FREQUENCY (MSPS)

TOTAL POWER

IAVDD

IDRVDD

Figure 57. AD9613-250 Power and Current vs. Sample Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9613 is placed in power-down mode.

In this state, the ADC typically dissipates 10 mW. During power-

down, the output drivers are placed in a high impedance state.

Asserting the PDWN pin low returns the AD9613 to its normal

operating mode. Note that PDWN is referenced to the digital

output driver supply (DRVDD) and should not exceed that

supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section and the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI, for additional details.

DIGITAL OUTPUTS

The AD9613 output drivers can be configured for either ANSI

LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.

As detailed in Application Note AN-877, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

Digital Output Enable Function (OEB)

The AD9613 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OEB pin or

through the SPI interface. If the OEB pin is low, the output data

drivers are enabled. If the OEB pin is high, the output data drivers

are placed in a high impedance state. This OEB function is not

intended for rapid access to the data bus. Note that OEB is

referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage.

When using the SPI interface, the data outputs of each channel

can be independently three-stated by using the output enable bar

bit (Bit 4) in Register 0x14. Because the output data is interleaved,

if only one of the two channels is disabled, the output data of

the remaining channel is repeated in both the rising and falling

output clock cycles.

Timing

The AD9613 provides latched data with a pipeline delay of 10 input

sample clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9613. These

transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9613 is 40 MSPS. At

clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9613 also provides data clock output (DCO) intended for

capturing the data in an external register. Figure 2 shows a timing

diagram of the AD9613 output modes.

ADC OVERRANGE (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 10 ADC clock. An overrange at the input is

indicated by this bit 10 clock cycles after it.

Table 11. Output Data Format

Input (V)

VIN+ − VIN−,

Input Span = 1.75 V p-p (V)

Offset Binary Output Mode

Twos Complement Mode (Default)

VIN+ − VIN–

Less than –0.875

0000 0000 0000

1000 0000 0000

VIN+ − VIN–

–0.875

0000 0000 0000

1000 0000 0000

VIN+ − VIN–

1000 0000 0000

0000 0000 0000

VIN+ − VIN–

+0.875

1111 1111 1111

0111 1111 1111

VIN+ − VIN–

Greater than +0.875

1111 1111 1111

0111 1111 1111

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