HT46R47 datasheet(13/45 Pages) HOLTEK

13 / 45 page

HT46R47

Rev. 1.40

July 18, 2001

Timer can be disabled by a ROM code option. If

the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

Once the internal oscillator (RC oscillator with

a period of 72ms/5V normally) is selected, it is

first divided by 256 (8-stage) to get the nominal

time-out period of approximately 18.6ms/5V.

This time-out period may vary with tempera-

tures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can

be realized and the maximum time-out period

is 2.3s/5V~4.7s/5V seconds. If the WDT oscilla-

tor is disabled, the WDT clock may still come

from the instruction clock and operate in the

same manner except that in the HALT state the

WDT may stop counting and lose its protecting

purpose. In this situation the logic can only be

restarted by external logic.

If the device operates in a noisy environment, us-

ing the on-chip RC oscillator (WDT OSC) is

strongly recommended, since the HALT will stop

the system clock.

The WDT overflow under normal operation will

initialize ²chip reset² and set the status bit

²TO². But in the HALT mode, the overflow will

initialize a ²warm reset², and only the PC and

SP are reset to zero. To clear the contents of

WDT, three methods are adopted; external re-

set (a low level to RES), software instruction

and a "HALT" instruction. The software in-

struction include ²CLR WDT² and the other set

-²CLR WDT1² and ²CLR WDT2². Of these two

types of instruction, only one can be active de-

pending on the ROM code option -²CLR WDT

times selection option².Ifthe ²CLR WDT² is se-

lected (i.e. CLRWDT times equal one), any exe-

cution of the ²CLR WDT² instruction will clear

the WDT. In the case that ²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times

equal two), these two instructions must be exe-

cuted to clear the WDT; otherwise, the WDT

may reset the chip as a result of time-out.

Power down operation - HALT

The HALT mode is initialized by the ²HALT²

instruction and results in the following...

· The system oscillator will be turned off but

the WDT oscillator keeps running (if the

WDT oscillator is selected).

· The contents of the on chip RAM and regis-

ters remain unchanged.

· WDT will be cleared and recounted again (if

the WDT clock is from the WDT oscillator).

· All of the I/O ports maintain their original sta-

tus.

· The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means

of an external reset, an interrupt, an external

falling edge signal on port A or a WDT overflow.

An external reset causes a device initialization

and the WDT overflow performs a ²warm re-

set². After the TO and PD flags are examined,

the reason for chip reset can be determined.

The PD flag is cleared by system power-up or

executing the ²CLR WDT² instruction and is

set when executing the ²HALT² instruction.

The TO flag is set if the WDT time-out occurs,

and causes a wake-up that only resets the PC

and SP; the others keep their original status.

The port A wake-up and interrupt methods can

be considered as a continuation of normal exe-

cution. Each bit in port A can be independently

selected to wake up the device by the ROM code

option. Awakening from an I/O port stimulus,

the program will resume execution of the next

instruction. If it is awakening from an inter-

rupt, two sequences may happen. If the related

interrupt is disabled or the interrupt is enabled

but the stack is full, the program will resume

execution at the next instruction. If the inter-

rupt is enabled and the stack is not full, the reg-

ular interrupt response takes place. If an

interrupt request flag is set to ²1² before enter-

ing the HALT mode, the wake-up function of

the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume normal operation.

In other words, a dummy period will be inserted

after wake-up. If the wake-up results from an

interrupt acknowledgment, the actual inter-

rupt subroutine execution will be delayed by

one or more cycles. If the wake-up results in the

next instruction execution, this will be executed

immediately after the dummy period is fin-

ished.

To minimize power consumption, all the I/O

pins should be carefully managed before enter-

ing the HALT status.

HT46R47 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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