LTC1871 datasheet(21/36 Pages) LINER

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LTC1871

The inductor ripple current is:

∆=

O MAX

MAX

χ •

–

.•

–.

()

10 39

And so the inductor value is:

kHz

IN MIN

MAX

∆

()

•

.•

•.

4 6

300

039

0 93

The component chosen is a 1

µH inductor made by

Sumida (part number CEP125-H 1ROMH) which has a

saturation current of greater than 20A.

5. With the input voltage to the IC bootstrapped to the

output of the power supply (5V), a logic-level MOSFET

can be used. Because the duty cycle is 39%, the

maximum SENSE pin threshold voltage is reduced from

its low duty cycle typical value of 150mV to approxi-

mately 140mV. Assuming a MOSFET junction tempera-

ture of 125

°C, the room temperature MOSFET RDS(ON)

should be less than:

DS ON

SENSE MAX

MAX

O MAX

()

(

)

()

•

–

••

.•

–.

•• .

≤

















=Ω

0 140

10 39

71 5

The MOSFET used was the Fairchild FDS7760A, which

has a maximum RDS(ON) of 8mΩ at 4.5V VGS, a BVDSS

of greater than 30V, and a gate charge of 37nC at 5V

VGS.

6. The diode for this design must handle a maximum DC

output current of 10A and be rated for a minimum

reverse voltage of VOUT, or 5V. A 25A, 15V diode from

On Semiconductor (MBRB2515L) was chosen for its

high power dissipation capability.

7. The output capacitor usually consists of a high valued

bulk C connected in parallel with a lower valued, low

ESR ceramic. Based on a maximum output ripple

voltage of 1%, or 50mV, the bulk C needs to be greater

than:

kHz

OUT

OUT MAX

OUT

≥=

=µ

()

.•

•

.•

•

001

0 01 5

300

466

The RMS ripple current rating for this capacitor needs

to exceed:

RMS COUT

O MAX

OIN MIN

IN MIN

()

(

)

()

•

–

•

–.

≥=

53 3

To satisfy this high RMS current demand, four 150

µF

Panasonic capacitors (EEFUEOJ151R) are required.

In parallel with these bulk capacitors, two 22

µF, low

ESR (X5R) Taiyo Yuden ceramic capacitors

(JMK325BJ226MM) are added for HF noise reduction.

Check the output ripple with a single oscilloscope

probe connected directly across the output capacitor

terminals, where the HF switching currents flow.

8. The choice of an input capacitor for a boost converter

depends on the impedance of the source supply and the

amount of input ripple the converter will safely tolerate.

For this particular design and lab setup a 100

µF Sanyo

Poscap (6TPC 100M), in parallel with two 22

µF Taiyo

Yuden ceramic capacitors (JMK325BJ226MM) is re-

quired (the input and return lead lengths are kept to a

few inches, but the peak input current is close to 20A!).

As with the output node, check the input ripple with a

single oscilloscope probe connected across the input

capacitor terminals.

PC Board Layout Checklist

1. In order to minimize switching noise and improve

output load regulation, the GND pin of the LTC1871

should be connected directly to 1) the negative termi-

nal of the INTVCC decoupling capacitor, 2) the negative

terminal of the output decoupling capacitors, 3) the

source of the power MOSFET or the bottom terminal of

the sense resistor, 4) the negative terminal of the input

capacitor and 5) at least one via to the ground plane

APPLICATIO S I FOR ATIO

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