SA1110 datasheet(13/406 Pages) INTEL

13 / 406 page

SA-1110 Developer’s Manual

xiii

11.12.6.8 Telecom Receive FIFO Overrun Status (TRO) (read/write,

nonmaskable interrupt) ...................................................................... 11–147

11.12.6.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only,

noninterruptible).................................................................................11–147

11.12.6.10Audio Receive FIFO Not Empty Flag (ANE) (read-only,

noninterruptible).................................................................................11–147

11.12.6.11Telecom Transmit FIFO Not Full Flag (TNF) (read-only,

noninterruptible).................................................................................11–148

11.12.6.12Telecom Receive FIFO Not Empty Flag (TNE) (read-only,

noninterruptible).................................................................................11–148

11.12.6.13Codec Write Completed Flag (CWC) (read-only, noninterruptible) .. 11–148

11.12.6.14Codec Read Completed Flag (CRC) (read-only, noninterruptible) ...11–148

11.12.6.15Audio Codec Enabled Flag (ACE) (read-only, noninterruptible) ....... 11–148

11.12.6.16Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible)...11–149

11.12.7 SSP Operation......................................................................................... 11–151

11.12.7.1 Frame Format .................................................................................... 11–151

11.12.7.2 Baud Rate Generation ....................................................................... 11–155

11.12.7.3 SSP Transmit and Receive FIFOs .................................................... 11–155

11.12.7.4 CPU and DMA Register Access Sizes .............................................. 11–156

11.12.7.5 Alternate SSP Pin Assignment .......................................................... 11–156

11.12.8 SSP Register Definitions ......................................................................... 11–156

11.12.9 SSP Control Register 0............................................................................ 11–156

11.12.9.1 Data Size Select (DSS) ..................................................................... 11–157

11.12.9.2 Frame Format (FRF) ......................................................................... 11–157

11.12.9.3 Synchronous Serial Port Enable (SSE) ............................................. 11–157

11.12.9.4 Serial Clock Rate (SCR) ....................................................................11–158

11.12.10SSP Control Register 1........................................................................... 11–159

11.12.10.1Receive FIFO Interrupt Enable (RIE)................................................ 11–159

11.12.10.2Transmit FIFO Interrupt Enable (TIE) ............................................... 11–159

11.12.10.3Loopback Mode (LBM) ..................................................................... 11–160

11.12.10.4Serial Clock Polarity (SPO)............................................................... 11–160

11.12.10.5Serial Clock Phase (SPH)................................................................. 11–160

11.12.10.6External Clock Select (ECS) .............................................................11–161

11.12.11SSP Data Register.................................................................................. 11–162

11.12.12SSP Status Register ............................................................................... 11–164

11.12.12.1Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)...... 11–164

11.12.12.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible).. 11–164

11.12.12.3SSP Busy Flag (BSY) (read-only, noninterruptible) .......................... 11–164

11.12.12.4Transmit FIFO Service Request Flag (TFS) (read-only,

maskable interrupt) ............................................................................ 11–164

11.12.12.5Receive FIFO Service Request Flag (RFS) (read-only,

maskable interrupt) ............................................................................ 11–165

11.12.12.6Receiver Overrun Status (ROR) (read/write,

nonmaskable interrupt) ...................................................................... 11–165

11.12.13MCP Register Locations ......................................................................... 11–166

11.12.14SSP Register Locations..........................................................................11–167

11.13

Peripheral Pin Controller (PPC) .................................................................. 11–167

11.13.1 PPC Operation......................................................................................... 11–167

11.13.2 PPC Register Definitions ......................................................................... 11–168

11.13.3 PPC Pin Direction Register...................................................................... 11–168

11.13.4 PPC Pin State Register ........................................................................... 11–170

11.13.5 PPC Pin Assignment Register ................................................................. 11–172

11.13.5.1 UART Pin Reassignment (UPR)........................................................ 11–172

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