SA1110 datasheet(39/406 Pages) INTEL

39 / 406 page

SA-1110 Developer’s Manual

3-3

ARM Implementation Options

3.2.3

Abort

An abort can be signalled by the internal memory-management unit, through a data breakpoint, or

by a reference to reserved memory. An abort indicates that the current memory access cannot be

completed or that a prespecified breakpoint address and (optionally) data pattern has been reached.

For instance, in a virtual memory system, the data corresponding to the current address may have

been moved out of memory onto a disk, and considerable processor activity may be required to

recover the data before the access can be performed successfully. The SA-1110 checks for an abort

during memory access cycles. When aborted, the SA-1110 responds in one of two ways:

1. If the abort occurred during an instruction prefetch (a prefetch abort), the prefetched

instruction is marked as invalid but the abort exception does not occur immediately. If the

instruction is not executed, for example, as a result of a branch being taken while it is in the

pipeline, no abort will occur. An abort will take place if the instruction reaches the head of the

pipeline and is about to be executed.

2. If the abort occurred during a data access (a data abort), the action depends on the instruction

type.

a. Single data transfer instructions (LDR, STR) will abort with no registers modified.

b. The swap instruction (SWP) is aborted as though it had not executed, though externally

the read access may take place.

c. Block data transfer instructions (LDM, STM) abort on the first access that cannot

complete. If write-back is set, the base is NOT updated. If the instruction would normally

have overwritten the base with data (for example, an LDM instruction with the base in the

transfer list), the original value in the base register is restored.

When either a prefetch or data abort occurs, the SA-1110 performs the following:

1. Saves the address of the aborted instruction plus 4 (for prefetch aborts) or 8 (for data aborts) in

R14_abt; saves CPSR in SPSR_abt.

2. Forces M 4:0 =10111 (abort mode) and sets the I bit in the CPSR.

3. Forces the PC to fetch the next instruction from either address 0x0C (prefetch abort) or address

0x10 (data abort).

To return after fixing the reason for the abort, use SUBS PC,R14_abt,#4 (for a prefetch abort) or

SUBS PC,R14_abt,#8 (for a data abort). This will restore both the PC and the CPSR, and retry the

aborted instruction.

The abort mechanism allows a demand paged virtual memory system to be implemented when

suitable memory management software is available. The processor is allowed to generate arbitrary

addresses, and when the data at an address is unavailable, the MMU signals an abort. The processor

traps into system software, which must work out the cause of the abort, make the requested data

available, and retry the aborted instruction. The application program needs no knowledge of the

amount of memory available to it, nor is its state in any way affected by the abort.

SA1110 Datasheet(PDF) 39 Page - Intel Corporation