VIA Technologies, Inc.

VT82C42

-1-

VT82C42 Keyboard Controller

Date : November 22, 1995

1. General Overview:

The VT82C42 is a compatible direct replacement for the Intel 80C42 BIOS version of the Keyboard

Controller. The VT82C42 is fully implemented by hardware logic so that it has a very fast response capability

for any command issued by the host. In addition to keyboard support, the VT82C42 also offers PS/2 mouse

designed by VIA technologies, which locks the mouse when the keylock function is initiated.

2. Features:

µm CMOS Technology.

3. Function Description:

The internal timer counting is based on an 8Mhz clock input from X1, X2 ( or X2, with X1 connected to

ground). After the deassertion of RESET#, the VT82C42 will drive high at pin P23 and pin P27. After 6

µs (6

x 8 clocks) of driving, the VT82C42 will check on pins T1 & P10; if both pins are low, then the VT82C42

will switch to PS/2 mode. Otherwise, the VT82C42 will remain in AT mode.

If the VT82C42 is in AT mode after the self test, then it will drive P24 and P25 low with all other ports high.

If the VT82C42 is in PS/2 mode, then it will drive P24, P25, P22, and P27 low with all other ports high. The

VT82C42 will not change its driving value until it receives the command "AA" from the host. When receiving

the command "AA" from the host, the VT82C42 will prepare a "55" in its output buffer and drive P24

(reflecting the internal OBF flag) high within 6 clocks. This response time is the typical active time for

internal IBF flag. After this initialization procedure, the VT82C42 will drive P26 low (AT mode) or drive P26

and P23 low (PS/2 mode) in order for the keyboard and mouse interface to receive data from keyboard or

mouse.

When the keyboard or mouse toggles the interface (KBCLK, KBDATA, MSCLK,MSDATA), the controller

receives data from the serial interface and stores the received data into its internal output buffer. If the

received data is from the keyboard, a scan code translation is executed before the data is sent to the output

buffer. The VT82C42 also raises P24 or P25 to indicate a output buffer full. The host is signaled to issue a

read command to the data port to read the received data out. When the VT82C42 receives data in the normal

mode (pin 25 on DIP40 or pin 28 on PLCC44 parts connected to VCC) and the status of P17 is low, then the

controller will not raise the P24, nor activate its internal OBF flag. It looks like the controller will consume the

income data itself. And if the data is from the mouse, the controller will still raise P25 to indicate that data is

PLCC44 parts connected to GND), the data from either keyboard or mouse will be prohibited from sending to

the host.